VLSI Test Principles and Architectures
Design for Testability
- 1st Edition - July 7, 2006
- Imprint: Morgan Kaufmann
- Authors: Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
- Language: English
- Paperback ISBN:9 7 8 - 1 - 4 9 3 3 - 0 0 8 6 - 0
- Hardback ISBN:9 7 8 - 0 - 1 2 - 3 7 0 5 9 7 - 6
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 4 7 4 7 9 - 3
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and… Read more
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Request a sales quoteThis book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
- Most up-to-date coverage of design for testability.
- Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
- Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
PRIMARY: Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.
SECONDARY: Undergraduate and graduate-level courses in Electronic Testing, Digital Systems Testing, Digital Logic Test & Simulation, and VLSI Design.
SECONDARY: Undergraduate and graduate-level courses in Electronic Testing, Digital Systems Testing, Digital Logic Test & Simulation, and VLSI Design.
Chapter 1 – Introduction
Chapter 2 – Design for Testability
Chapter 3 – Logic and Fault Simulation
Chapter 4 – Test Generation
Chapter 5 – Logic Built-In Self-Test
Chapter 6 – Test Compression
Chapter 7 – Logic Diagnosis
Chapter 8 – Memory Testing and Built-In Self-Test
Chapter 9 – Memory Diagnosis and Built-In Self-Repair
Chapter 10 – Boundary Scan and Core-Based Testing
Chapter 11 – Analog and Mixed-Signal Testing
Chapter 12 – Test Technology Trends in the Nanometer Age
Chapter 2 – Design for Testability
Chapter 3 – Logic and Fault Simulation
Chapter 4 – Test Generation
Chapter 5 – Logic Built-In Self-Test
Chapter 6 – Test Compression
Chapter 7 – Logic Diagnosis
Chapter 8 – Memory Testing and Built-In Self-Test
Chapter 9 – Memory Diagnosis and Built-In Self-Repair
Chapter 10 – Boundary Scan and Core-Based Testing
Chapter 11 – Analog and Mixed-Signal Testing
Chapter 12 – Test Technology Trends in the Nanometer Age
- Edition: 1
- Published: July 7, 2006
- No. of pages (Hardback): 808
- Imprint: Morgan Kaufmann
- Language: English
- Paperback ISBN: 9781493300860
- Hardback ISBN: 9780123705976
- eBook ISBN: 9780080474793
LW
Laung-Terng Wang
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
Affiliations and expertise
SynTest Technologies, Inc., Sunnyvale, CA, USACW
Cheng-Wen Wu
Affiliations and expertise
National Tsing Hua University, Hsinchu, Taiwan.XW
Xiaoqing Wen
Affiliations and expertise
Kyushu Institute of Technology, Fukuoka, Japan.Read VLSI Test Principles and Architectures on ScienceDirect