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Verification Techniques for System-Level Design
- 1st Edition - October 17, 2007
- Authors: Masahiro Fujita, Indradeep Ghosh, Mukul Prasad
- Language: English
- Paperback ISBN:9 7 8 - 0 - 1 2 - 4 0 5 4 6 1 - 5
- Hardback ISBN:9 7 8 - 0 - 1 2 - 3 7 0 6 1 6 - 4
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 5 5 3 1 3 - 9
This book will explain how to verify SoC (Systems on Chip) logic designs using “formal” and “semiformal” verification techniques. The critical issue to be addressed is whether the… Read more
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Request a sales quoteThis book will explain how to verify SoC (Systems on Chip) logic designs using “formal” and “semiformal” verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional” verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
• First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.
PRIMARY: Practitioners/Researchers in System-Level Design and Verification; Design Engineers at companies such as Synopsis, Cadence, Intel.
SECONDARY: Reference for graduate-level courses in SoC design and verification.
SECONDARY: Reference for graduate-level courses in SoC design and verification.
- No. of pages: 256
- Language: English
- Edition: 1
- Published: October 17, 2007
- Imprint: Morgan Kaufmann
- Paperback ISBN: 9780124054615
- Hardback ISBN: 9780123706164
- eBook ISBN: 9780080553139
MF
Masahiro Fujita
*Spent 15 years at Fujitsu research laboratories.
*Research on synthesis and verification of digital systems for more than 25 years
*Full professor at VLSI Design and Education Center in the University of Tokyo
Affiliations and expertise
Professor, VLSI Design & Education Center, University of Tokyo, Japan.IG
Indradeep Ghosh
Indradeep Ghosh received the Bachelor of Technology degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, India, in 1993, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, New Jersey, in 1995 and 1998, respectively.
Since 1998 he has been a member of research staff in at Fujitsu Laboratories of America, Sunnyvale, California. He has authored or co-authored more that 40 technical articles in international journals and conferences and holds 6 US patents. He has given numerous presentations in international conferences and workshops. In Fujitsu he has been involved in design verification and testing of industrial systems that are currently in production. His research interests include testing, verification, and validation of hardware and software systems. He is senior member of the IEEE and a member of the ACM.
Affiliations and expertise
Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.MP
Mukul Prasad
Mukul Prasad:
Mukul Prasad received the Bachelor of Technology degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India, in 1995, and the Ph.D. degree in Electrical Engineering & Computer Sciences from the University of California at Berkeley in 2001.
Since 2001 he has been a member of the research staff in the Trusted Systems Innovation group at Fujitsu Laboratories of America in Sunnyvale, California. His doctoral thesis and his subsequent research has involved the development and application of verification technologies such as Satisfiability solvers. His work has received a Best Paper Award at the Design Automation & Test in Europe Conference (DATE 2002). His current research addresses various problems in system-level design validation. He has co-authored more than 20 technical papers and presented three tutorials at international conferences and jointly holds 3 U.S. patents in the area of formal validation.
Affiliations and expertise
Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.Read Verification Techniques for System-Level Design on ScienceDirect