Silicon-On-Insulator (SOI) Technology

Part I: Silicon-on-insulator (SOI) materials and manufacture

1. Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology

• Abstract:
• 1.1 Introduction
• 1.2 SOI wafer fabrication technologies: an overview
• 1.3 SOI volume-fabrication process
• 1.4 SOI wafer structures and characterization
• 1.5 Direct wafer bonding: wet surface cleaning techniques
• 1.6 Characterization of direct bonding mechanisms
• 1.7 Alternative surface preparation processes for Si and SiO₂ direct bonding
• 1.8 Mass production of SOI substrates by ion implantation, bonding and splitting: Smart Cut™ technology
• 1.9 Fabrication of more complex SOI structures
• 1.10 Fabrication of heterogeneous structures
• 1.11 Conclusion
• 1.12 Acknowledgments
• 1.13 References

2. Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors

• Abstract:
• 2.1 Introduction
• 2.2 Conventional characterization techniques
• 2.3 Characterization of SOI wafers using the pseudo-metal oxide semiconductor field effect transister (MOSFET) technique
• 2.4 Developments in the pseudo-MOSFET technique
• 2.5 Conventional methods for the characterization of FD MOSFETs
• 2.6 Advanced methods for the characterization of FD MOSFETs
• 2.7 Characterization of ultrathin SOI MOSFETs
• 2.8 Characterization of multiple-gate MOSFETs
• 2.9 Characterization of nanowire FETs
• 2.10 Conclusions
• 2.11 Acknowledgments
• 2.12 References

3. Modeling the performance of short-channel fully depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs)

• Abstract:
• 3.1 Introduction
• 3.2 The development of SOI MOSFET modeling
• 3.3 A 1-D compact capacitive model for a SOI MOSFET
• 3.4 A 2-D analytical model for a SOI MOSFET
• 3.5 Modeling of dual gate and other types of SOI MOSFET architecture
• 3.6 References

4. Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions

• Abstract:
• 4.1 Introduction
• 4.2 PDSOI technology and devices
• 4.3 Circuit solutions: digital circuits
• 4.4 Circuit solutions: static random access memory (SRAM) circuits
• 4.5 SRAM margining: PDSOI example
• 4.6 Future trends
• 4.7 References

5. Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology

• Abstract:
• 5.1 Introduction
• 5.2 Planar FDSOI technology
• 5.3 V_T adjustment on FDSOI: channel doping, gate stack engineering and ground planes
• 5.4 Substrate requirements for FDSOI CMOS devices: BOX and channel thicknesses
• 5.5 Strain options on FDSOI
• 5.6 Performance without and with back bias
• 5.7 Conclusion
• 5.8 Acknowledgements
• 5.9 References

6. Silicon-on-insulator (SOI) junctionless transistors

• Abstract:
• 6.1 Introduction
• 6.2 Device physics
• 6.3 Models for the junctionless transistor
• 6.4 Performance comparison with trigate field effect transistors (FETs)
• 6.5 Beyond the classical SOI nanowire architecture
• 6.6 Conclusion
• 6.7 Acknowledgments
• 6.8 References

7. Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs)

• Abstract:
• 7.1 Introduction
• 7.2 SOI FinFET device performance
• 7.3 SOI FinFET substrate optimization
• 7.4 Process and statistical variability of FinFETs
• 7.5 Summary
• 7.6 References

8. Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

• Abstract:
• 8.1 Introduction
• 8.2 Statistical variability in planar fully depleted SOI devices
• 8.3 Statistical aspects of reliability
• 8.4 Fin-on-oxide field effect transistors (FinFETs) on SOI
• 8.5 Summary and future trends
• 8.6 References

9. Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology

• Abstract:
• 9.1 Introduction
• 9.2 ESD characterization in SOI devices: SOI transistors
• 9.3 ESD characterization in SOI devices: SOI diodes
• 9.4 ESD characterization in SOI devices: fin-on-oxide field effect transistors (FinFETs) and FinDiodes
• 9.5 ESD characterization in SOI devices: fully depleted SOI (FDSOI) devices
• 9.6 ESD network optimization in SOI devices
• 9.7 Conclusion
• 9.8 References

Part II: Silicon-on-insulator (SOI) devices and applications

10. Silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) for radio frequency (RF) and analogue applications

• Abstract:
• 10.1 Introduction
• 10.2 Current performance of RF devices
• 10.3 Limiting factors in MOSFET performance
• 10.4 Schottky barrier (SB) MOSFETs
• 10.5 Ultra-thin body ultra-thin BOX (UTBB) MOSFETs
• 10.6 RF performance of a multi-gate MOSFET: fin-on-oxide field effect transistor (FinFET)
• 10.7 High-resistivity silicon (HR-Si) substrate for SOI technology
• 10.8 Conclusions
• 10.9 Acknowledgements
• 10.10 References

11. Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits for ultralow power (ULP) applications

• Abstract:
• 11.1 Introduction: the importance of ultralow power devices
• 11.2 Minimizing power consumption of CMOS circuits
• 11.3 Issues on V_dd scaling to improve the energy efficiency of CMOS circuits
• 11.4 Developing SOI devices with small variability and adaptive bias control
• 11.5 Modelling variability
• 11.6 Device design for ultralow-voltage operation
• 11.7 Assessing variability in fully depleted silicon-on-insulator (FDSOI) devices
• 11.8 Assessing the reliability of FDSOI devices
• 11.9 Circuit design of FDSOI devices
• 11.10 Future trends
• 11.11 Acknowledgment
• 11.12 References

12. 3D integration of silicon-on-insulator (SOI) integrated circuits (ICs) for improved performance

• Abstract:
• 12.1 Introduction
• 12.2 3D integration using Cu–Cu bonding: generic flow techniques
• 12.3 3D integration using Cu–Cu bonding: face-to face silicon layer stacking
• 12.4 3D integration using Cu–Cu bonding: back-to-face silicon layer stacking
• 12.5 3D integration using oxide bonding: the MIT Lincoln Laboratory’s ‘face down’ stacking technique
• 12.6 3D integration using oxide bonding: IBM’s ‘face up’ stacking technique
• 12.7 3D integration using oxide bonding: the sequential 3D process
• 12.8 Advanced bonding technology: Cu–Cu bonding
• 12.9 Advanced bonding technology: dielectric bonding
• 12.10 Summary
• 12.11 Acknowledgements
• 12.12 References

13. Silicon-on-insulator (SOI) technology for photonic integrated circuits (PICs)

• Abstract:
• 13.1 Introduction
• 13.2 Silicon (on insulator) photonics
• 13.3 Photonic building blocks in SOI
• 13.4 Device tolerances and compensation techniques
• 13.5 Advanced stacks for silicon photonics
• 13.6 Applications of silicon photonics
• 13.7 Conclusion
• 13.8 References

14. Silicon-on-insulator (SOI) technology for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) sensors

• Abstract:
• 14.1 Introduction
• 14.2 SOI MEMS/NEMS device structures and principles of operation
• 14.3 SOI MEMS/NEMS design
• 14.4 SOI MEMS/NEMS processing technologies
• 14.5 SOI MEMS/NEMS fabrication
• 14.6 Conclusion
• 14.7 References