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See MIPS Run
- 1st Edition - February 18, 1999
- Imprint: Morgan Kaufmann
- Author: Dominic Sweetman
- Language: English
- Paperback ISBN:9 7 8 - 1 - 5 5 8 6 0 - 4 1 0 - 0
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 5 1 6 9 2 - 9
The versatile offspring of an extended family of multiple chip companies, today's MIPS chips are everywhere. They power everything from videogames, network routers, laser pr… Read more
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The versatile offspring of an extended family of multiple chip companies, today's MIPS chips are everywhere. They power everything from videogames, network routers, laser printers, set-top boxes, and high-performance workstations. This book brings together this extraordinary proliferation of form and functionality, offering embedded systems programmers and designers unique, eminently practical insights into MIPS. It covers how MIPS started, the principles at the root of the RISC revolution, the full details of the MIPS instruction set, and how these details together constitute a full operating system ready to be put to work in hundreds of ways.
If you're programming embedded systems and need to understand the chips at the deepest level, or even if you're just curious, you're sure to find what you need in this book. It's all here, from the nuts and bolts of a programming reference to the big picture that only a true expert can deliver. So buy the book. Take it home. Step inside. And see MIPS run.
* Written by an independent consultant whose business is understanding MIPS architecture and embedded systems programming.* Addresses the evolution of MIPS technology, giving you a solid foundation for successful designs and implementations.* Provides an in-depth, easy-to-use guide to the MIPS instruction set, including special attention to processor control and assembler mnemonics for every instruction.* Covers everything from MIPS I to MIPS IV, with appendices devoted to the optional MIPS 16 instruction set and V/MDMX.
MIPS programmers, embedded system programmers and designers.
ContentsForewordPrefaceStyle and LimitsConventionsAcknowledgmentsRISCs and MIPS1.1 Pipelines1.1.1 What Makes a Pipeline Inefficient?1.1.2 The Pipeline and Caching1.2 The MIPS Five-Stage Pipeline1.3 RISC and CISC1.4 Great MIPS Chips of the Past and Present1.4.1 R2000 to R30001.4.2 R6000: A Diversion1.4.3 The R4000 Revolution1.4.4 R5000 and R100001.5 MIPS Compared with CISC Architectures1.5.1 Constraints on MIPS Instructions1.5.2 Addressing and Memory Accesses1.5.3 Features You Won't Find1.5.4 A Feature You Might Not Expect1.5.5 Programmer-Visible Pipeline EffectsMIPS Architechture2.1 A Flavor of MIPS Assembly Language2.2 Registers2.2.1 Conventional Names and Uses of General-Purpose Registers2.3 Integer Multiply Unit and Registers2.4 Loading and Storing: Addressing Modes2.5 Data Types in Memory and Registers2.5.1 Integer Data Types2.5.2 Unaligned Loads and Stores2.5.3 Floating-point Data in Memory2.6 Synthesized Instructions in Assembly Language2.7 MIPS I to MIPS IV: 64-Bit (and Other) Extensions2.7.1 To 64 Bits2.7.2 Who Needs 64 Bits?2.7.3 Regarding 64 Bits and No Mode Switch: Data in Registers2.7.4 Other Innovations in MIPS III2.8 Basic Address Space2.8.1 Addressing in Simple Systems2.8.2 Kernel vs. User Privelege Levels2.8.3 The Full Picture: The 64-Bit View of the Memory Map2.9 Pipeline HazardsCoprocessor 0: MIPS Processor Control3.1 CPU Control Instructions3.2 What Registers Are Relevant When?3.3 Encodings of Standard CPU Control Registers3.3.1 Processor ID (PRId) Register3.3.2 Status Register (SR)3.3.3 Cause Register3.3.4 Exception Return Address (EPC) Register3.3.5 Bad Virtual Address (BadVaddr) Register3.4 Control Registers for the R4000 CPU and Followers3.4.1 Count/Compare Registers: The R4000 Timer3.4.2 Config Register: R4x00 Configuration3.4.3 Load-Linked Address (LLAddr) Register3.4.4 Debugger Watchpoint (WatchLo/WatchHi) RegistersCaches for MIPS4.1 Caches and Cache Management4.2 How Caches Work4.3 Write-Through Caches in Early MIPS CPUs4.4 Write-Back Caches in Recent MIPS CPUs4.5 Other Choices in Cache Design4.6 Managing Caches4.7 Secondary and Tertiary Caches4.8 Cache Configurations for MIPS CPUs4.9 Programming R3000-Style Caches4.9.1 Using Cache Isolation and Swapping4.9.2 Initializing and Sizing4.9.3 Invalidation4.9.4 Testing and Probing4.10 Programming R4000-Style Caches4.10.1 CacheERR, ERR, and ErrorEPC Registers: Cache Error Handling4.10.2 The Cache Instruction4.10.3 Cache Sizing and Figuring Out Configuration4.10.4 Initialization Routines4.10.5 Invalidating or Writing Back a Region of Memory in the Cache4.11 Cache Efficiency4.12 Reorganizing Software to Influence Cache Effieciency4.13 Write Buffers and When You Need to Worry4.13.1 Implementing wbflush4.14 More About MIPS Caches4.14.1 Multiprocessor Cache Features4.14.2 Cache AliasesExceptions, Interrupts, and Initialization5.1 Precise Exceptions5.2 When Exceptions Happen5.3 Exception Vectors: Where Exception Handling Starts5.4 Exception Handling: Basics5.5 Returning from an Exception5.6 Nesting Exceptions5.7 An Exception Routine5.8 Interrupts5.8.1 Interrupt Resources in MIPS CPUs5.8.2 Implementing Interrupt Priority5.8.3 Atomicity and Atomic Changes to SR5.8.4 Critical Regions with Interrupts Enable: Semaphores the MIPS Way5.9 Starting Up5.9.1 Probing and Recognizing Your CPU5.9.2 Bootstrapping Sequences5.9.3 Starting Up an Application5.10 Emulating InstructionsMemory Management and the TLB6.1 Memory Management in Big Computers6.1.1 Basic Process Layout and Protection6.1.2 Mapping Process Addresses to Real Memory6.1.3 Paged Mapping Preferred6.1.4 What We Really Want6.1.5 Origins of the MIPS Design6.2 MIPS TLB Facts and Figures6.3 MMU Registers Described6.3.1 EntryHi, EntryLo, and PageMask6.3.2 Index6.3.3 Random6.3.4 Wired6.3.5 Context and Xcontext6.4 MMU Control Instructions6.5 Programming in the TLB6.5.1 How Refill Happens6.5.2 Using ASIDs6.5.3 The Random Register and Wired Entries6.6 Memory Translation: Setup6.7 TLB Exception Sample Code6.7.1 The 32-Bit User TLB Miss Exception Handler6.7.2 TLB Miss Exception Handler for R4x00 CPU6.7.3 XTLB Miss Handler6.8 Keeping Track of Modified Pages (Simulating "Dirty Bits")6.9 Memory Translation and 64-Bit Pointers6.10 Everyday Use of the MIPS TLB6.11 Memory Management in a Non-Unix OSFloating-Point Support7.1 A Basic Description of Floating Point7.2 The IEEE754 Standard and Its Background7.3 How IEEE Floating-Point Numbers Are Stored7.3.1 IEEE Mantissa and Normalization7.3.2 Reserved Exponent Values for Use with Strange Values7.3.3 MIPS FP Data Formats7.4 MIPS Implementation of IEEE7547.4.1 Need for FP Trap Handler and Emulator in All MIPS CPUs7.5 Floating-Point Registers7.5.1 Conventional Names and Uses of Floating-Point Registers7.6 Floating-Point Exceptions/Interrupts7.7 Floating-Point Control: The Control/Status Register7.8 Floating-Point Implementation/Revision Register7.9 Guide to FP Instructions7.9.1 Load/Store7.9.2 Move Between Registers7.9.3 Three-Operand Arithmetic Operations7.9.4 Multiply-Add Operations7.9.5 Unary (Sign-Changing) Operations7.9.6 Conversion Operations7.9.7 Conditional Branch and Test Instructions7.10 Instruction Timing Requirements7.11 Instruction Timing for Speed7.12 Initialization and Enabling on Demand7.13 Floating-Point EmulationComplete Guide to the MIPS Instruction Set8.1 A Simple Example8.2 Assembler Mnemonics and What They Mean8.2.1 U and non-U Mnemonics8.2.2 Divide Mnemonics8.2.3 Inventory of Instructions8.3 Floating-Point Instructions8.4 Peculiar Instructions and Their Purposes8.4.1 Load Left/Load Right: Unaligned Load and Store8.4.2 Load-Linked/Store-Conditional8.4.3 Conditional Move Instructions8.4.4 Branch-Likely8.4.5 Integer Multiply-Accumulate and Multiply-Add Instructions8.4.6 Floating-Point Multiply-Add Instructions8.4.7 Multiple FP Condition Bits8.4.8 Prefetch8.4.9 Sync: A Load/Store Barrier8.5 Instruction Encodings8.5.1 Fields in the Instruction Encoding Table8.5.2 Notes on the Instruction Encoding Table8.5.3 Encodings and Simple Implementation8.6 Instructions by Functional Group8.6.1 No-op8.6.2 Register/Register Moves8.6.3 Load Constant8.6.4 Arithmetical/Logical8.6.5 Integer Multiply, Divide, and Remainder8.6.6 Integer Multiply-Accumulate8.6.7 Loads and Stores8.6.8 Jumps, Subroutine Calles, and Branches8.6.9 Breakpoint and Trap8.6.10 CP0 Functions8.6.11 Floating Point8.6.12 ATM and Floating PointAssembler Language Programming9.1 A Simple Example9.2 Syntax Overview9.2.1 Layout, Delimiters, and Identifiers9.3 General Rules for Instructions9.3.1 Computational Instructions: Three, Two, and One9.3.2 Immediates: Computational Instructions with Constants9.3.3 Regarding 64-Bit and 32-Bit Instructions9.4 Addressing Modes9.4.1 Gp-Relative Addressing9.5 Assembler Directives9.5.1 Selecting Sections9.5.2 Practical Problem Layout Including Stack and Heap9.5.3 Data Definition and Alignment9.5.4 Symbol-Binding Attributes9.5.5 Function Derivatives9.5.6 Assembler Control (.set)9.5.7 Compiler/Debugger Support9.5.8 Additional Directives in SGI Assembly LanguageC Programming on MIPS10.1 The Stack, Subroutine Linkage, and Parameter Passing10.2 Stack Argument Structure10.3 Using Registers to Pass Arguments10.4 Examples from the C Library10.5 An Exotic Example: Passing Structures10.6 Passing a Variable Number of Arguments10.7 Returning a Value from a Function10.8 Evolving Register-Use Standards: SGI's n32 and n6410.9 Stack Layouts, Stack Frames, and Helping Debuggers10.9.1 Leaf Functions10.9.2 Nonleaf Functions10.9.3 Frame Pointers for More Complex Stack Requirements10.10 Variable Number of Arguments and stdargs10.11 Sharing Functions between Different Threads and Shared Library Problems10.11.1 Sharing Code in Single-Address-Space Systems10.11.2 Sharing Library Code in the MIPS ABI10.12 An Introduction to Compiler Optimization10.12.1 Common Optimizations10.12.2 Optimizer-Unfriendly Code and How to Avoid It10.12.3 The Limits of Optimization10.13 Hints about Device Access from C10.13.1 Using "Volatile" to Inhibit Destructive Optimization10.13.2 Unaligned Data from CPortability Considerations and C Code11.1 Porting to MIPS: A Checklist of Frequently Encountered Problems11.2 An Idealized Porting Process11.2.1 Three Porting Choices11.2.2 Fixing Up Dependencies11.2.3 Isolating Nonportable Code11.2.4 When to Use an Assembler11.3 Portable C and Language Standards11.4 C Library Functions and POSIX11.5 Data Representations and Alignment11.6 Endianess: Words, Bytes, and Bit Order11.6.1 Endianness and the Programmer11.6.2 Endianness: The Pictures and the Intellectual Problem11.6.3 Endianness: The Hardware Problem11.6.4 Wiring a Connection Between Opposite-Endian Camps11.6.5 Wiring an Endianness-Configurable Connection11.6.6 Software to Cope with Both-Endianness of a MIPS CPU11.6.7 Portability and Endianness-Independent Code11.6.8 Endianness and Foreign Data11.6.9 False Cures and False Prophets for Endianness Problems11.7 What Can Go Wrong with Caches and How to Stop It11.7.1 Cache Management and DMA Data11.7.2 Cache Management and Writing Instructions11.7.3 Cache Management and Uncached/Write-Through Data11.8 Different Implementations of MIPSSoftware Examples12.1 Starting Up MIPS12.2 MIPS Cache Management12.2.1 Cache Operations: 32-bit MIPS Before Cache Instructions12.2.2 Cache Operations: After MIPS III and Cache Instructions12.3 MIPS Exception Handling12.3.1 xcption: What It Does For Programmers12.3.2 xcption: C Interface Code12.3.3 xcption: Low-Level Module12.4 MIPS Interrupts12.5 Tuning for MIPSAppendix A Instruction Timing and OptimizationA.1 Avoiding Hazards: Making Code CorrectA.2 Avoiding Interlocks to Increase PerformanceA.3 Multiply Unit Hazards: Early Modifications of Hi and LoA.4 Avoiding Coprocessor Hazards: How Many No-ops?A.5 Copreocessor Instruction/Instruction SchedulingA.6 Coprocessor Flags and InstructionsAppendix B Assembler Language SyntaxAppendix C Object CodeC.1 ToolsC.2 Sections and SegmentsC.3 ECOFF (RISC/OS)C.3.1 File HeaderC.3.2 Optional a.out HeaderC.3.3 Example LoaderC.3.4 Further ReadingC.4 ELF (MIPS ABI)C.4.1 File HeaderC.4.2 Program HeaderC.4.3 Example LoaderC.4.4 Further ReadingC.5 Object Code ToolsAppendix D Evolving MIPSD.1 MIPS16D.1.1 Special Encodings and Instructions in MIPS 16D.1.2 MIPS16 EvaluatedD.2 MIPS V/MDMXD.2.1 Can Compilers Use Multimedia Instructions?D.2.2 Applications for MDMXD.2.3 Applications for MIPS VD.2.4 Likely Success of MDMX/MIPS VMIPS GlossaryReferences
- Edition: 1
- Published: February 18, 1999
- Imprint: Morgan Kaufmann
- Language: English
DS
Dominic Sweetman
Dominic Sweetman is a member of the last generation of programmers who could reasonably hope to understand computer systems from bottom to top. His rich career began with low-level coding, progressing from OS development to LANs to distributed systems. Dominic is an experienced designer and developer of hardware systems, CPUs, networks, and operating systems. He was a founder member of Whitechapel Workstations, and in 1988 founded Algorithmics, a MIPS consulting firm of which he is the director. Dominic lives with his partner, two grown-up children and three cats in north London.
Affiliations and expertise
MIPS Technologies