LIMITED OFFER
Save 50% on book bundles
Immediately download your ebook while waiting for your print delivery. No promo code needed.
Networks on Chips
Technology and Tools
- 1st Edition - July 20, 2006
- Authors: Giovanni De Micheli, Luca Benini
- Editor: Luca Benini
- Language: English
- Hardback ISBN:9 7 8 - 0 - 1 2 - 3 7 0 5 2 1 - 1
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 4 7 3 5 6 - 7
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly… Read more
Purchase options
Institutional subscription on ScienceDirect
Request a sales quoteThe design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution.
This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
* Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends
* An integrated presentation not currently available in any other book
* A thorough introduction to current design methodologies and chips designed with NoCs
* An integrated presentation not currently available in any other book
* A thorough introduction to current design methodologies and chips designed with NoCs
Primary: Researchers/Practitioners in Multiprocessor Systems on Chips; Networks on Chips. VLSI design companies (ST Microelectronics, Arteris, etc.) involved currently with implementing NoCs on silicon.
Secondary: Graduate-level courses in System on Chip design.
Secondary: Graduate-level courses in System on Chip design.
I. Introduction and Motivation
Why on chip networks?
State of the art
Taxonomy
Technology trends
II. Architectures for NoCs
Direct vs indirect networks
Topologies
Standard architectures and formal properties
Ad hoc networks
III. Physical network layer
Wiring issues
Physical routing
Signalling
Driver/receiver design
Noise immunity
Shielding
IV. Data-link layer and encoding
Medium access control
Data encoding
Error correcting codes: theory and practice
Arbitration issues
V. Switching and Routing in NoCs
Packets, flits.
Data forwarding schemes
Routing: algorithms and routers
QoS guarantees
VI. Software for NoCs
Programming paradigms: shared medium vs message passing
Middleware issues. layering and software encapsulation
Application layer issue and network-aware compilation
VII. Tools for NoC Design
Analysis and Synthesis of NoCs
Present tools (Bones, Xpipes) and future outlook
VIII. On-Chip multiprocessors
High-performance monolithic multiprocessors
Network issues
IX. SoCs based on NoCs
Examples of other design chips using NoCs
Why on chip networks?
State of the art
Taxonomy
Technology trends
II. Architectures for NoCs
Direct vs indirect networks
Topologies
Standard architectures and formal properties
Ad hoc networks
III. Physical network layer
Wiring issues
Physical routing
Signalling
Driver/receiver design
Noise immunity
Shielding
IV. Data-link layer and encoding
Medium access control
Data encoding
Error correcting codes: theory and practice
Arbitration issues
V. Switching and Routing in NoCs
Packets, flits.
Data forwarding schemes
Routing: algorithms and routers
QoS guarantees
VI. Software for NoCs
Programming paradigms: shared medium vs message passing
Middleware issues. layering and software encapsulation
Application layer issue and network-aware compilation
VII. Tools for NoC Design
Analysis and Synthesis of NoCs
Present tools (Bones, Xpipes) and future outlook
VIII. On-Chip multiprocessors
High-performance monolithic multiprocessors
Network issues
IX. SoCs based on NoCs
Examples of other design chips using NoCs
- No. of pages: 408
- Language: English
- Edition: 1
- Published: July 20, 2006
- Imprint: Morgan Kaufmann
- Hardback ISBN: 9780123705211
- eBook ISBN: 9780080473567
LB
Luca Benini
Affiliations and expertise
University of Bologna, Italy.GD
Giovanni De Micheli
Affiliations and expertise
École Polytechnique Fédérale de Lausanne, SwitzerlandLB
Luca Benini
Affiliations and expertise
University of Bologna, Italy.Read Networks on Chips on ScienceDirect