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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design
- 1st Edition - May 21, 2019
- Authors: Chenming Hu, Sourabh Khandelwal, Yogesh Singh Chauhan, Thomas Mckay, Josef Watts, Juan Pablo Duarte, Pragya Kushwaha, Harshit Agarwal
- Language: English
- Paperback ISBN:9 7 8 - 0 - 0 8 - 1 0 2 4 0 1 - 0
- eBook ISBN:9 7 8 - 0 - 0 8 - 1 0 2 4 0 2 - 7
Industry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation… Read more
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Request a sales quoteIndustry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation of the FDSOI device, explaining not only how FDSOI enables further scaling, but also how it offers unique possibilities in circuits. Following chapters cover the industry standard compact model BSIM-IMG for FDSOI devices. The book addresses core surface-potential calculations and the plethora of real devices and potential effects. Written by the original developers of the industrial standard model, this book is an excellent reference for the new BSIM-IMG compact model for emerging FDSOI technology.
The authors include chapters on step-by-step parameters extraction procedure for BSIM-IMG model and rigorous industry grade tests that the BSIM-IMG model has undergone. There is also a chapter on analog and RF circuit design in FDSOI technology using the BSIM-IMG model.
- Provides a detailed discussion of the BSIM-IMG model and the industry standard simulation model for FDSOI, all presented by the developers of the model
- Explains the complex operation of the FDSOI device and its use of two independent control inputs
- Addresses the parameter extraction challenges for those using this model
Semiconductor engineers, Materials Scientists, Circuit Designers, Researchers in electronic devices and circuits
- No. of pages: 258
- Language: English
- Edition: 1
- Published: May 21, 2019
- Imprint: Woodhead Publishing
- Paperback ISBN: 9780081024010
- eBook ISBN: 9780081024027
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Chenming Hu
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching – the Berkeley Distinguished Teaching Award.
Affiliations and expertise
TSMC Distinguished Chair Professor Emeritus, University of California Berkeley, USASK
Sourabh Khandelwal
Sourabh Khandelwal is an Associate Professor at Macquarie University. He is the lead author of two industry standard compact models: ASM-HEMT for GaN RF and power technology, and ASM-ESD for silicon ESD applications. He has also co-authored BSIM-CMG, BSIM-IMG and BSIM6 compact models during his tenure at the BSIM group at the University of California Berkeley. Dr Khandelwal has published 3 books and over 150 research papers. He regularly serves as consultant to multi-national semiconductor companies.
Affiliations and expertise
Associate Professor, Macquarie University, Sydney, AustraliaYC
Yogesh Singh Chauhan
Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Affiliations and expertise
Chair Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, IndiaTM
Thomas Mckay
Director of RF Innovation at Globalfoundries, USA
Affiliations and expertise
Director of RF Innovation, Globalfoundaries, USAJW
Josef Watts
Principal Member of Technical Staff at Globalfoundries USA
Affiliations and expertise
Principal Member of Technical Staff, Globalfoundries, USAJD
Juan Pablo Duarte
Juan Pablo Duarte Sepúlveda obtained his Ph.D. at the University of California, Berkeley in 2018. He received his B.Sc. in 2010 and his M.Sc. in 2012, both in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at the Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers on nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper: Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.
Affiliations and expertise
University of California, Berkeley, USAPK
Pragya Kushwaha
Pragya Kushwaha is currently a Postdoctoral Researcher with Prof. Chenming Hu in the BSIM Device Modeling Group at University of California, Berkeley. She received her PhD degree from Indian Institute of Technology Kanpur, India in 2017. She has authored several national and international research papers in the area of semiconductor device modeling and characterization. During her PhD, she has developed a complete RF compact model for FDSOI transistors under the frame work of industry standard BSIM-IMG compact model. Her current research interests include modeling, simulation, and characterization of advanced semiconductor devices such as nanowires, NCFETs, PD/FDSOIs, FinFETs, tunnel FETs, high-voltage FETs, and bulk MOSFETs.
Affiliations and expertise
Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USAHA
Harshit Agarwal
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization.
Affiliations and expertise
Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USARead Industry Standard FDSOI Compact Model BSIM-IMG for IC Design on ScienceDirect