Handbook of Multilevel Metallization for Integrated Circuits

1. Introduction 1.0 MLM Terminology and Structure 2.0 What are the Uses of Metal Layers in an Integrated Circuit? 3.0 Why Use Multiple Layers of Metal 4.0 Trends in Multilevel Metallization 5.0 Methodology for Developing an MLM System 6.0 Summary References2. Silicides and Contacts for ULSI 1.0 Introduction 2.0 Silicides for Application to Salicide and Polycide 3.0 Sputtered Barrier Materials Between Al and Si or Silicide 4.0 CVD Barrier Materials 5.0 Local Interconnects and Multilevel Metallization 6.0 Conclusion and Future Trends References3. Aluminum Based Multilevel Metallizations in VLSI/ULSICs 1.0 Introduction 2.0 Requirements in Multilevel Metallizations 3.0 Applications of AIX in Multilevel Metallizations and Key Problems 4.0 Properties of Al, AIX and Related Materials 5.0 Current Status of Al-Based Multilevel Metallizations 6.0 Key Reliability Issues in AIX-Based Multilevel Metallizations and Some Solutions 7.0 Future Directions 8.0 Summary References4. Inorganic Dielectrics 1.0 Introduction 2.0 CVD Processes 3.0 Deposition Equipment 4.0 Spin On Dielectrics 5.0 Film Characterization 6.0 Doped Glasses 7.0 Intermetal Layer Dielectric 8.0 Passivation Layer 9.0 Summary References5. Organic Dielectrics in Multilevel Metallization of Integrated Circuits 1.0 General Introduction 2.0 Historical Perspective 3.0 Fundamental Chemistry of Organic Dielectrics 4.0 Processing of Polymer Films 5.0 Process Integration with Organic Dielectrics 6.0 Reliability 7.0 Performance Advantages of Organic Dielectrics 8.0 Future Trends References6. Planarization Techniques 1.0 Why Planarize? 2.0 Concepts 3.0 Thermal Flow of Borophosphosilicate Glass (BPSG Films) 4.0 Planarization with Sacrificial Photoresist 5.0 Planarization Using Spin-On-Glass 6.0 Deposition-Etchback Techniques 7.0 Planarization by Chemical-Mechanical Polishing 8.0 Gap Filling Using CVD Ozone-TEOS Oxides 9.0 Outlook References7. Lithography and Etch Issues for a Multilevel Metallization System 1.0 Introduction 2.0 Introduction to Pattern Transfer Technology 3.0 Etch References8. Electro- and Stress-Migration in MLM Interconnect Structures 1.0 Introduction 2.0 Theory of Electromigration 3.0 Electromigration in Thin Films 4.0 Measurement of Temperature and Current Density in MLM Structures 5.0 Electromigration Measurement Techniques 6.0 Life Test Method 7.0 Damage Formation in Multilevel Metallization 8.0 Stress-Induced Void Formation References9. Multilevel Metallization Test Vehicle 1.0 Introduction 2.0 Process Control 3.0 Defectivity and Yield Enhancement Structures 4.0 Test Structures for Reliability 5.0 Summary References10. Manufacturing and Analytic Methods 1.0 Introduction (Business Perspectives) 2.0 Performance Drivers 3.0 Architecture 4.0 Unit Processes 5.0 Key Design Rules 6.0 Design for Manufacture 7.0 Equipment Integration 8.0 Challenges and Requirements 9.0 Control and Analytic Capability 10.0 Summary References11. Characterization Techniques for VLSI Multilevel Metallization 1.0 Introduction 2.0 Imaging Techniques 3.0 Surface Analysis 4.0 Thin Film 'Bulk' Analysis Techniques 5.0 Conclusion References12. Electronic Packaging and its Influences on Integrated Circuit Design and Processing 1.0 Overview 2.0 Package Types 3.0 Fundamentals of Packaging 4.0 Integrated Circuit Design/Structure and Packaging Influences References13. Future Interconnect Systems 1.0 Introduction 2.0 Metallization Trend in the Next Decade 3.0 Summary Perspective on Interconnection Technology References Index