BSIM–SOI Industry-Standard Compact Model
Surface Potential-Based FET Model for RFIC Design
- 1st Edition - July 1, 2026
- Latest edition
- Authors: Chetan Kumar Dabhi, Debashish Nandi, Dinesh Rajasekharan, Chenming Hu, Yogesh Singh Chauhan, Ananth Sundaram
- Language: English
BSIM–SOI Industry-Standard Compact Model: Surface Potential-Based FET Model for RFIC Design provides complete coverage of compact modeling and design techniques specific to… Read more
BSIM–SOI Industry-Standard Compact Model: Surface Potential-Based FET Model for RFIC Design provides complete coverage of compact modeling and design techniques specific to SOI transistors. It is designed to be the first comprehensive guide that thoroughly explains the industry-standard BSIM-SOI compact model, along with the unique modeling and RF design techniques necessary for the accurate extraction and implementation of the industry standard BSIM-SOI model. BSIM-SOI is the most widely used compact model in the semiconductor industry. This book will equip designers, engineers, and researchers with the knowledge and tools required to optimize SOI-based circuit performance and system integration. The book explains the fundamental surface-potential calculations and addresses various real device effects, such as floating body, self-heating, and dynamic depletion effects, and layout influences, to accurately replicate realistic device behavior. Additionally, the step-by-step parameter extraction procedures for the BSIM-SOI model are outlined and the results of benchmark tests are also presented. This book will be a valuable reference for the expanding field of SOI technology, catering specifically to circuit designers, device engineers, academic researchers, and students.
- Serves as an invaluable and practical reference for comprehending the operational intricacies and underlying physics of SOI devices
- Comprehensively covers all facets of the BSIM-SOI model, offering insights directly from the model developers themselves
- Offers detailed insights into and solutions for the challenges associated with extracting parameters from SOI devices due to factors such as conventional and gate-induced floating body effects, dynamic depletion effects, etc
- Provides clear guidance (focusing primarily on the modeling process) on the measurement data needed to extract BSIM-SOI model parameters
- Discusses RF switch and power amplifier design and links this to device parameters via physics-based simulation models
Circuit designers (analog and digital IC; RF), modeling and PDK engineers, device engineers, graduate students and researchers working on circuit design
1. General overview of SOI models and technology trends
2. Core model formulation
3. Real device effects
4. Terminal charges and capacitances
5. Leakage currents
6. Noise models in BSIM-SOI
7. Body contact parasitics – modeling approach
8. Self-Heating and Temperature Effects
9. Cutting-Edge RF Modeling and Validation Techniques
10. Integrating BSIM-SOI Models in Analog, Digital, and RF Designs
11. Parameter Extraction
12. Model Quality testing
2. Core model formulation
3. Real device effects
4. Terminal charges and capacitances
5. Leakage currents
6. Noise models in BSIM-SOI
7. Body contact parasitics – modeling approach
8. Self-Heating and Temperature Effects
9. Cutting-Edge RF Modeling and Validation Techniques
10. Integrating BSIM-SOI Models in Analog, Digital, and RF Designs
11. Parameter Extraction
12. Model Quality testing
- Edition: 1
- Latest edition
- Published: July 1, 2026
- Language: English
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Chetan Kumar Dabhi
Chetan Kumar Dabhi is a Staff Engineer at pSemi Corporation, San Diego, United States. He specializes in developing and supporting industry-standard compact models for diverse semiconductor devices, including SOI FETs, FinFETs, and Bulk FETs (BSIM-SOI, BSIM-IMG, BSIM-BULK, and BSIM4).
Affiliations and expertise
Staff Engineer, pSemi Corporation, San Diego, USADN
Debashish Nandi
Debashish Nandi is a Researcher in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. His research focuses on compact modelling and device characterization of various nanoscale devices, primarily SOI MOSFETs for RF applications for advanced communication standards like 5G and 6G.
Affiliations and expertise
Researcher, Department of Electrical Engineering, Indian Institute of Technology Kanpur, IndiaDR
Dinesh Rajasekharan
Dinesh Rajasekharan is a Postdoctoral Researcher in the BSIM group at the University of California Berkeley, United States. His research covers semiconductor device compact model development, neuromorphic computing using emerging semiconductor devices, and using neural networks in electronics applications.
Affiliations and expertise
Postdoctoral Researcher, University of California Berkeley, USACH
Chenming Hu
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching – the Berkeley Distinguished Teaching Award.
Affiliations and expertise
TSMC Distinguished Chair Professor Emeritus, University of California Berkeley, USAYC
Yogesh Singh Chauhan
Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Affiliations and expertise
Chair Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, IndiaAS
Ananth Sundaram
Ananth Sundaram is a Deputy Director at GlobalFoundries, Bengaluru, India. He is a technology professional with experience in semiconductor modeling, design, and measurement.
Affiliations and expertise
Deputy Director, GlobalFoundries, Bengaluru, India