VHDL Coding and Logic Synthesis with Synopsys

List of Figures. List of Tables. List of Examples. Preface. Acknowledgement. Trademarks. I. VHDL CODING1. Introduction. 1.1 Conventional Design - Schematic Capture1.2 Hardware Description Language1.3 VHDL Design Structure1.4 Component Instantiation Within a VHDL Design Structure1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure1.5.1 Structural VHDL1.5.2 Behavioral VHDL1.5.3 RTL Code1.6 Usage of Library Declarations in VHDL Design Structure2. VHDL Simulation and Synthesis Flow. 3. Synthesizable Code for Basic Logic Components.3.1 AND Logic3.2 OR Logic3.3 NOT Logic3.4 NAND Logic3.5 NOR Logic3.6 Tristate Buffer Logic3.7 Complex Logic Gate3.8 Latch3.8.1 Acoiding Latches In Your Code3.9 Flip Flop3.10 Decoder3.11 Encoder3.12 Multiplexer3.13 Priority Encoder3.14 Memory Cell3.15 Adder3.16 Component Inference4. Signal Versus Variable. 4.1 Variable4.2 Signal4.3 When to Use Signal and When to Use Variable4.4 Usage of Loopback Signal5. Examples of Complex Synthesizable Code.5.1 Shifter5.2 Counter5.3 Memory Module5.4 Car Traffic Controller6. Pipeline Microcontroller Synthesizable Design. 6.1 Intruction Set Definition6.2 Architechtural Definition6.3 Pipeline Definition6.4 Microarchitechture Definition for the Pipeline Microcontroller6.4.1 Predecode Block6.4.2 Decode Block6.4.3 Register File Block6.4.4 Execute BlockII. LOGIC SYNTHESIS WITH SYNOPSYS. 7. Timing Considerations in Design. 7.1 Setup Timing Violation7.2 Hold Timiing Violation7.3 Setup/Hold Timing Considerations in Synthesis7.4 Microarchitechural Tweaks for Fixing Setup Time Violations7.4.1 Logic Duplication to Generate Independent Paths7.4.2 Logic Duplication Prior to Selection of Later Arrival Signal7.4.3 Balancing of Logic between Flip-Flops7.4.4 Priority Decoding Versus Multiplex Decoding7.5 Microarchitechtural Tweaks for Fixing Hold Time Violations7.6 Asynchronous/False Paths7.7 Multicycle Paths8. VHDL Synthesis with Timing Constraints. 8.1 Introduction to Design Compiler8.2 IUsing Design Compiler for Synthesis8.3 Performance Tweaks8.3.1 Compilation With 'map_effort high' Option8.3.2 Group Critical Paths Together and Give Them a Weight Factor8.3.3 Logical Flattening of a Design8.3.4 Characterizing Submodules8.3.5 Register Balancing8.3.6 Usage of FSM Compiler to Optimize Finite State Machine8.3.7 Choosing High-Speed Implementation for High-Level Functional Module8.3.8 Balancing of Logic Trees with Heavy Loading8.4 Area Optimization in Synthesis Tweaks8.4.1 Do Not Use Combinational Logic as Individual Blocks8.4.2 Do Not Use Glue Logic between Modules8.4.3 set_max_area Attribute8.5 Fixing Hold-Time Violations in Synopsys8.6 Misc Synthesis Commands Generally Used8.7 Top-Down and Bottoms-Up Compilation 9. GTECH Instantiation. 10. DesignWare Library. 10.1 Creating Your Own Designware Library11. Testability Issues in Synthesis. 11.1 Multiplexed Flip-Hop Scan Style11.2 Using Synopsys Test Compiler for Scan Insertion12. FPGA Synthesis. 13. Synthesis Links to Layout. 13.1 Forward-Annotations13.2 Wireload Models13.3 Floorplanning a Design13.4 Post Layout Optimization14. Design Guideline to Follow for Efficient Synthesis. 15. Appendix A (STD_LOGIC_1164 Library). 16. Appendix B (Shifter Synthesis Results). 17. Appendix C (Counter Synthesis Results).18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6).Glossary. Bibliography. Index.