The Student's Guide to VHDL
- 1st Edition - January 1, 1998
- Imprint: Morgan Kaufmann
- Author: Peter J. Ashenden
- Language: English
- Paperback ISBN:9 7 8 - 1 - 5 5 8 6 0 - 5 2 0 - 6
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 5 7 2 8 2 - 6
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware sy… Read more
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Request a sales quoteVHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
This new book provides a tutorial
introduction to the fundamental modeling features of VHDL and shows how the features are used for the design of digital systems.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
* On-line resources include code for case studies. * Numerous exercises that are coded for difficulty and expected solution time. * Solutions to the level one exercises are included in the book for self-testing.* An appendix citing the differences between the 1987 standard and the 1993 standard which is described in the book.
- Preface
- 1 Fundamental Concepts
- 1.1 Modeling Digital Systems
- 1.2 Domains and Levels of Modeling
- 1.3 Modeling Languages
- 1.4 VHDL Modeling Concepts
- Elements of Behavior
- Elements of Structure
- Mixed Structural and Behavioral Models
- Test Benches
- Analysis, Elaboration and Execution
- 1.5 Learning a New Language: Lexical Elements and Syntax
- Lexical Elements
- Syntax Descriptions
- Exercises
- 2 Scalar Data Types and Operations
- 2.1 Constants and Variables
- Constant and Variable Declarations
- Variable Assignment
- 2.2 Scalar Types
- Type Declarations
- Integer Types
- Floating-Point Types
- Physical Types
- Enumeration Types
- 2.3 Type Classification
- Subtypes
- Type Qualification
- Type Conversion
- 2.4 Attributes of Scalar Types
- 2.5 Expressions and Operators
- Exercises
- 3 Sequential Statements
- 3.1 If Statements
- 3.2 Case Statements
- 3.3 Null Statements
- 3.4 Loop Statements
- Exit Statements
- Next Statements
- While Loops
- For Loops
- Summary of Loop Statements
- 3.5 Assertion and Report Statements
- Exercises
- 4 Composite Data Types and Operations
- 4.1 Arrays
- Multidimensional Arrays
- Array Aggregates
- Array Attributes
- 4.2 Unconstrained Array Types
- Strings
- Bit Vectors
- Standard-Logic Arrays
- String and Bit-String Literals
- Unconstrained Array Ports
- 4.3 Array Operations and Referencing
- Array Slices
- Array Type Conversions
- 4.4 Records
- Record Aggregates
- Exercises
- 5 Basic Modeling Constructs
- 5.1 Entity Declarations
- 5.2 Architecture Bodies
- Concurrent Statements
- Signal Declarations
- 5.3 Behavioral Descriptions
- Signal Assignment
- Signal Attributes
- Wait Statements
- Delta Delays
- Transport and Inertial Delay Mechanisms
- Process Statements
- Concurrent Signal Assignment Statements
- Concurrent Assertion Statements
- Entities and Passive Processes
- 5.4 Structural Descriptions
- Component Instantiation and Port Maps
- 5.5 Design Processing
- Analysis
- Design Libraries, Library Clauses and Use Clauses
- Elaboration
- Execution
- Exercises
- 6 Subprograms
- 6.1 Procedures
- Return Statement in a Procedure
- 6.2 Procedure Parameters
- Signal Parameters
- Default Values
- Unconstrained Array Parameters
- Summary of Procedure Parameters
- 6.3 Concurrent Procedure Call Statements
- 6.4 Functions
- Functional Modeling
- Pure and Impure Functions
- The Function Now
- 6.5 Overloading
- Overloading Operator Symbols
- 6.6 Visibility of Declarations
- Exercises
- 7 Packages and Use Clauses
- 7.1 Package Declarations
- Subprograms in Package Declarations
- Constants in Package Declarations
- 7.2 Package Bodies
- 7.3 Use Clauses
- 7.4 The Predefined Package Standard
- Exercises
- 8 Resolved Signals
- 8.1 Basic Resolved Signals
- Composite Resolved Subtypes
- Summary of Resolved Subtypes
- 8.2 IEEE Std_Logic_1164 Resolved Subtypes
- 8.3 Resolved Signals and Ports
- Resolved Ports
- Driving Value Attribute
- 8.4 Resolved Signal Parameters
- Exercises
- 9 Generic Constants
- 9.1 Parameterizing Behavior
- 9.2 Parameterizing Structure
- Exercises
- 10 Components and Configurations
- 10.1 Components
- Component Declarations
- Component Instantiation
- Packaging Components
- 10.2 Configuring Component Instances
- Basic Configuration Declarations
- Configuring Multiple Levels of Hierarchy
- Direct Instantiation of Configured Entities
- Generic and Port Maps in Configurations
- Deferred Component Binding
- Exercises
- A The Predefined Package Standard
- B IEEE Standard 1164
- C VHDL Syntax
- Index to Syntax Rules
- C.1 Design File
- C.2 Library Unit Declarations
- C.3 Declarations and Specifications
- C.4 Type Definitions
- C.5 Concurrent Statements
- C.6 Sequential Statements
- C.7 Interfaces and Associations
- C.8 Expressions
- D Differences Between VHDL-87 and VHDL-93
- Lexical Differences
- Syntactic Differences
- Semantic Differences
- Differences in the Standard Environment
- VHDL-93 Facilities Not in VHDL-87
- E Answers to Exercises
- References
- Index
- Edition: 1
- Published: January 1, 1998
- Imprint: Morgan Kaufmann
- Language: English
- Paperback ISBN: 9781558605206
- eBook ISBN: 9780080572826
PA
Peter J. Ashenden
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Affiliations and expertise
Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia