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RISC-V Microprocessor System-On-Chip Design
- 1st Edition - January 1, 2025
- Authors: David Harris, James Stine, Sarah Harris
- Language: English
- Paperback ISBN:9 7 8 - 0 - 3 2 3 - 9 9 4 9 8 - 9
- eBook ISBN:9 7 8 - 0 - 3 2 3 - 9 9 4 9 9 - 6
RISC-V Microprocessor System-On-Chip Design is intended for a graduate or undergraduate course in microprocessor design. The reader will learn to design and optimize microproc… Read more
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Request a sales quoteRISC-V Microprocessor System-On-Chip Design is intended for a graduate or undergraduate course in microprocessor design. The reader will learn to design and optimize microprocessors and use them in a system-on-chip, applying contemporary design and verification tools. Much of the book describes detailed designs and tradeoffs for the functional blocks in and around a processor. RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background and will explain concepts from operating systems, VLSI, and memory systems as necessary. High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons. The book comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancilliary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.
- The first book covering detailed design of all components of a nontrivial microprocessor
- Provides detailed explanation of implementation of RISC-V microprocessors
- Uses open-source SystemVerilog code and test cases for the entire processor, including single-issue and superscalar cores, multicore, all extensions (including multiplication/division, floating point, and atomic memory operations), and common peripherals
- Enables users to build scripts to implement the processor on the open-source Skywater process
Senior-level elective or graduate course in the field of computer processor design in most electrical or computer engineering or CS programs. Navstem estimates US enrollment in digital integrated circuit courses (CMOS/VLSI) at 8,800 students per year.A secondary academic audience includes a portion of senior undergraduate and graduate courses in computer architecture, which Navstem estimates at 10,000 students per year.
1. Introduction
Part 1: RISC-V Architecture
2. RISC-V Architecture
3. Assembly Language Programming
4. C Programming
Part 2: RISC-V Microarchitecture
5. Microarchitecture Overview
6. Survey of Microarchitectures
7. RISC-V Pipelined Microarchitecture
8. Privileged Operations
9. AHB Interface
10. Virtual Memory
11. Branch Prediction
12. RISC-V Superscalar Microarchitecture
13. RISC-V Threaded Microarchitecture
14. Extensions: Compressed Instructions
15. Extensions: Multiplication and Division
16. Extensions: Floating Point
17. Extensions: Atomic Operations
18. More Bus Interfaces
19. Peripherals
20. Multicore
21. SIMD
22. Vector
23. Bit Manipulation
24. Crypto
Part 3: Validation
25. Logic Verification
26. Performance Validation: Benchmarking
27. Linux Boot
Part 4: Implementation
28. FPGA Implementation
29. CMOS for Microarchitects
30. CMOS Implementation
31. Silicon Debug
Part 1: RISC-V Architecture
2. RISC-V Architecture
3. Assembly Language Programming
4. C Programming
Part 2: RISC-V Microarchitecture
5. Microarchitecture Overview
6. Survey of Microarchitectures
7. RISC-V Pipelined Microarchitecture
8. Privileged Operations
9. AHB Interface
10. Virtual Memory
11. Branch Prediction
12. RISC-V Superscalar Microarchitecture
13. RISC-V Threaded Microarchitecture
14. Extensions: Compressed Instructions
15. Extensions: Multiplication and Division
16. Extensions: Floating Point
17. Extensions: Atomic Operations
18. More Bus Interfaces
19. Peripherals
20. Multicore
21. SIMD
22. Vector
23. Bit Manipulation
24. Crypto
Part 3: Validation
25. Logic Verification
26. Performance Validation: Benchmarking
27. Linux Boot
Part 4: Implementation
28. FPGA Implementation
29. CMOS for Microarchitects
30. CMOS Implementation
31. Silicon Debug
- No. of pages: 600
- Language: English
- Edition: 1
- Published: January 1, 2025
- Imprint: Morgan Kaufmann
- Paperback ISBN: 9780323994989
- eBook ISBN: 9780323994996
DH
David Harris
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.
Affiliations and expertise
Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USAJS
James Stine
James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library.
Affiliations and expertise
School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, OK, USASH
Sarah Harris
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.
Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.
Affiliations and expertise
Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA