Resource Efficient LDPC Decoders
From Algorithms to Hardware Architectures
- 1st Edition - December 5, 2017
- Latest edition
- Authors: Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz
- Language: English
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from al… Read more
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Description
Description
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.
The reader will learn:
- Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
- How to reduce computational complexity and power consumption using computer aided design techniques
- All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs
Key features
Key features
- Provides extensive treatment of LDPC decoding algorithms and hardware implementations
- Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
- Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis
Readership
Readership
Electrical and electronic engineers in academia and industry involved in the design of communication circuits; Research and development engineers in various government research organizations. Postgraduate research students (PhD and Masters) engaged in research in telecommunications and electronic engineering
Table of contents
Table of contents
Abbreviations1.Introduction1.1. Error correction in digital communication1.2. Forward error correction codesReferences2. Overview of LDPC codes2.1. Origin of LDPC codes2.2. Types of LDPC codes2.2.1. Regular and irregular codes2.2.2. Random and pseudo-random codes2.2.3. Structured and unstructured codes2.3. Terminologies in LDPC codes2.3.1. LDPC code parameters2.3.2. Simulation parameters2.3.3. Performance metrics2.4. Summary References3. Structure and flexibility of LDPC codes3.1. Common construction techniques3.1.1. Progressive edge growth algorithm3.1.2. Quasi-cyclic algorithm3.1.3. Spatially-coupled codes3.1.4. Repeat-accumulate codes3.2. Flexible matrices3.2.1. Structure of the matrix3.2.2. Construction technique3.2.3. Standard matrix configurations3.2.4. Visual analysis3.2.5. Performance analysis3.3. SummaryReferences4. LDPC decoding algorithms4.1. Standard decoding algorithms4.1.1. Bit-Flip algorithm4.1.2. Sum-Product algorithm4.1.3. Min-Sum algorithm4.1.4. Stochastic algorithm4.2. Reduced complexity algorithms4.2.1. Simplified message passing4.2.2. Modified Min-Sum4.3. Performance analysis of simplified algorithms4.3.1.Extraction of optimized parameters4.3.2.Performance comparison4.4.SummaryReferences5. LDPC decoder architectures5.1. Most common hardware architectures5.1.1. Fully- parallel5.1.2. Fully-serial5.1.3. Partially-parallel5.2. Literature review of LDPC decoders5.3. SummaryReferences6. Hardware implementation of LDPC decoder6.1. Decoder design methodology6.1.1. Design and implementation 6.1.2. Performance measurement6.2. Prototyping LDPC codes in hardware6.3. Implementation of hardware efficient decoder6.3.1. Fully-parallel architecture 6.3.2. Partially-parallel architecture6.3.3. Performance analysis6.4. Design space exploration6.4.1. Decoding performance6.4.2. Hardware performance6.5. SummaryReferences7. LDPC decoders in multimedia communication7.1. Image communication using LDPC codes7.2. Performance analysis7.2.1. Quality of the reconstructed BMP images7.2.2. Quality of the reconstructed JPEG images7.2.3. Reconstructed JPEG images for various decoders7.3. SummaryReferences8. Prospective LDPC applications8.1. Wireless communication8.2. Optical communication8.3. Flash memory devicesReferencesAppendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulationAppendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureAppendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture
Product details
Product details
- Edition: 1
- Latest edition
- Published: December 5, 2017
- Language: English
About the authors
About the authors
VC
Vikram Arkalgud Chandrasetty
SA