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Readings in Computer Architecture
- 1st Edition - September 9, 1999
- Editors: Mark D. Hill, Norman P. Jouppi, Gurindar S. Sohi
- Language: English
- Paperback ISBN:9 7 8 - 1 - 5 5 8 6 0 - 5 3 9 - 8
- eBook ISBN:9 7 8 - 0 - 0 8 - 0 5 7 3 6 4 - 9
Thanks to the continued exponential advances in semiconductor design and the demands of evolving and emerging application domains, the field of computer architecture has never be… Read more
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Request a sales quoteThanks to the continued exponential advances in semiconductor design and the demands of evolving and emerging application domains, the field of computer architecture has never been more dynamic. This, the first major book of computer architecture readings in over two decades, captures this dynamism and reveals Computer Architecture's rich history of practice.
This is much more than a simple collection of papers. The editors have carefully selected the most influential primary sources in specific areas of inquiry that, taken together, present the critical issues of the entire discipline. These include issues in technology, implementation, economics, evaluation methods, instruction set design, instruction level parallelism, dataflow/multithreading, memory systems, input/output systems, single-instruction multiple data parallelism, and multiple-instruction multiple data parallelism. In addition, you'll find the editors' thoughtful, focused introductions to each area, providing the context and background necessary for understanding the significance and lasting impact of these papers.
The primary sources and insightful commentary contained in this book provide foundational knowledge for computer architects as well as for those who design supporting system software and compilers. This is an excellent resource for practitioners, instructors, students, and researchers.
- Includes more than 50 influential papers spanning four decades of computer architecture research and development
- Selected, edited, and introduced by three eminent researchers and educators in the field.
- Demonstrates the value of primary sources by showing how forgotten design ideas of the past are often rediscovered when new needs or constraints emerge.
Graduate students and researchers in computer architecture, professional hardware designers and system software developers
PREFACECHAPTER 1 - Classic Machines: Technology, Implementation, and EconomicsG. M. AMDAHL, G. A. BLAAUW, F. P. BROOKS, JR., "Architecture of the IBM System/360," IBM Journal of Research and Development, , April 1964. J. E. THORNTON " Parallel Operation in the Control Data 6600," Fall Joint Computers Conference, , vol. 26, pp. 33-40, 1961. R. M. RUSSELL, "The Cray-1 Computer System", Comm. ACM, 21, 1 (January 1978), 63-72.J. KOLODZEY, "Cray-1 Computer Technology", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, p181-187, June 1981. G. MOORE, "Cramming More Components onto Integrated Circuits", Electronics, p114-117, April 1965.S. MAZOR, "The History of the Microcomputer - Invention and Evolution", Proc. IEEE Dec '95, 1601-1607.CHAPTER 2 - MethodsG. M. AMDAHL, "Validity of the Single-Processor Approach to Achieving Large Scale Computing Capabilities", AFIPS Conference Proceedings, (April 1967), 483-485. M. D. HILL and A. J. SMITH, "Evaluating Associativity in CPU Caches", IEEE Trans. on Computers, C-38, 12 (December 1989), 1612-1630. J. S. EMER and D. W. CLARK, "A Characterization of Processor Performance in the VAX-11/780", Proc. Eleventh International Symposium on Computer Architecture, Ann Arbor, MI (June 1984), 301-310. CHAPTER 3 - Instruction SetsW. A. WULF, "Compilers and Computer Architecture", IEEE Computer, 14, 7 (July 1981), 41-48. G. RADIN "The 801 Minicomputer," Proc. Symposium on Architectural Support for Programming Languages and Operating Systems, March 1982, 39-47. D. A. PATTERSON and D. R. DITZEL, "The Case for the Reduced Instruction Set Computer," ACM Computer Architecture News, 8, 6, 15 October 1980, 25-33. R. P. COLWELL, C. Y. HITCHCOCK, E. D. JENSEN, H. M. BRINKLEY SPRUNT, C. P. KOLLAR, "Computers, Complexity, and Controversy," IEEE Computer, vol. 18, no. 9, September 1985. J. CRAWFORD, "Architecture of the Intel 80386," Proceedings of ICCD , pp. 155-160, October 1986. S. MAHLKE, R. HANK, J. MCCORMICK, D. AUGUST, W. HWU, "A Comparison of Full and Partial Predicated Execution Support for ILP Processors", Proc. 22nd Annual Symposium on Computer Architecture (June 1995), 138-150. CHAPTER 4 - Instruction Level Parallelism (ILP)D. W. ANDERSON, F. J. SPARACIO and R. M. TOMASULO, "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", IBM Journal of Research and Development January 1967. J. E. SMITH and A. R. PLESZKUN, "Implementing Precise Interrupts in Pipelined Processors", IEEE Trans. on Computers, C-37, 5 (May 1988), 562-573. J. E. SMITH, "A Study of Branch Prediction Strategies", Proc. Eighth Annual Symposium on Computer Architecture (May 1981), 135-148. T.-Y. YEH and Y. N. PATT, "Two-Level Adaptive Branch Prediction," Proc. 24th Annual Workshop on Microprogramming (MICRO-24), Albuquerque, NM, (December 1991). Y. N. PATT, W. W. HWU and M. SHEBANOW, "HPS, A New Microarchitecture: Introduction and Rationale," Proc. 18th Annual Workshop on Microprogramming, Pacific Grove, CA (December 1985), 103-108. G. S. SOHI and S. VAJAPEYAM, "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors", Proc. 14th Annual Symposium on Computer Architecture (June 1987), 27-34. G. F. GROHOSKI, "Machine Organization of the IBM RISC System/6000 processor," IBM Journal of Research and Development, 34, 1 (January 1990), 37-58. K. C. YEAGER, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, 16, 2, April 1996, 28-40. B. R. RAU and J. A. FISHER, "Instruction-Level Parallel Processing: History, Overview, and Perspective", The Journal of Supercomputing,, 7, 1, (??? 1993), 9-50. Reprinted in Rau and Fisher (ed.), "Instruction-Level Parallelism, Kluwer Academic Publishers, 1993 CHAPTER 5 - Dataflow and MultithreadingJ. B. DENNIS and D. P. Misunas, "A Preliminary Architecture for a Basic Data-Flow Processor," Proc. 2nd Annual Symposium on Computer Architecture, Computer Architecture News, 3, 4 (December 1974), 126-132, ACM. ARVIND and R. S. NIKHIL, "Executing a Program on the MIT Tagged-Token Dataflow Architecture", IEEE Trans. on Computers, 39, 3 (March 1990), 300-318. B. SMITH, "Architecture and Applications of the HEP Multiprocessor Computer System", Proc. of the Int. Soc. for Opt. Engr. (1981), 241-248. D. M. TULLSEN, S. J. EGGERS, J. S. EMER, H. M. LEVY, J. L. LO and R. L. STAMM, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Proc. 23rd Annual Symposium on Computer Architecture (May 1996), 191-202. CHAPTER 6 - Memory SystemsM. V. WILKES, "Slave Memories and Dynamic Storage Allocation", IEEE Trans. on Electronic Computers, EC-14, 2 (April 1965), 270-271. J. S. LIPTAY, "Structural Aspects of the System/360 Model 85, Part II: The Cache", IBM Systems Journal,, 7, 1 (1968), 15-21). D. KROFT, "Lockup-Free Instruction Fetch/Prefetch Cache Organization", Proc. Eighth Symposium on Computer Architecture (May 1981), 81-87. J. R. GOODMAN, "Using Cache Memory to Reduce Processor-Memory Traffic", Proc. Tenth International Symposium on Computer Architecture, Stockholm, Sweden (June 1983), 124-131. N. P. JOUPPI, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers", Proc. 17th Annual Symposium on Computer Architecture, Computer Architecture News, 18, 2 (June1990), 364-373, ACM. T. KILBURN, D. B. G. EDWARDS, M. J. LANIGAN, F. H. SUMNER, "One-Level Storage System", IRE Transactions, EC-11, 2, (April 1962), 223-235. D. W. CLARK and J. S. EMER, "Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement", ACM Trans. on Computer Systems, 3, 1 (February 1985), 31-62. W. WANG, J.-L. BAER and H. M. LEVY, "Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy", Proc. 16th Annual International Symposium on Computer Architecture, Jerusalem (June 1989), 140-148. CHAPTER 7 - I/O: Storage Systems, Networks, and GraphicsM. SMOTHERMAN, "A Sequencing-based Taxonomy of I/O Systems and Review of Historical Machines", ACM Computer Architecture News 17:5, (September 1989), pgs 5-15. Storage SystemsC. RUEMMLER and J. WILKES, "An Introduction to Disk Drive Modeling", IEEE Computer vol 27 #3, March 1994, pgs 17-28. D. A. PATTERSON, G. GIBSON and R. H. KATZ, "A Case for Redundant Arrays of Inexpensive Disks (RAID)", Proc. ACM SIGMOD Conference, Chicago, Illinois (June 1988). NetworksR. METCALFE and D. BOGGS, "Ethernet: Distributed Packet Switching for Local Computer Networks." Communications of the ACM, 19(7):395-404. L. NI and P. MCKINLEY, "A Survey of Wormhole Routing Techniques in Direct Networks", IEEE Computer, February 1993, vol 26 #2, pgs 62-76. GraphicsK. AKERLY, "Reality Engine Graphics", SIGGRAPH '93 Proceedings, pp 109-116. CHAPTER 8 - Single-Instruction Multiple Data (SIMD) ParallelismM. J. FLYNN, " Very High-Speed Computing Systems", Proceedings of the IEEE , vol. 54, no. 12, December 1966. D. J. KUCK and R. A. STOKES, "The Burroughs Scientific Processor (BSP)", IEEE Trans. on Computers , vol. C-31, pp. 363-376, May 1982. M. GOKHALE, B. HOLMES, K. IOBST, "Processing in Memory: The Terasys Massively Parallel PIM Array", IEEE Computer, 28, 4 (April 1995), 23-31. CHAPTER 9 - Multiprocessors and MulticomputersW. A. WULF and S. P. HARBISON, "Reflections in a pool of processors/An experience report on C.mmp/Hydra", Proc. National Computer Conference (AFIPS) (June 1978). L. LAMPORT, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. on Computers, C-28, 9 (September 1979), 690-691. L. M. CENSIER and P. FEAUTRIER, "A New Solution to Coherence Problems in Multicache Systems", IEEE Transactions on Computers, C-27, 12 (December 1978), 1112-1118. D. LENOSKI, J. LAUDON, K. GHARACHORLOO, W. WEBER, A. GUPTA, J. HENNESSY, M. HOROWITZ and M. LAM, "The Stanford DASH Multiprocessor", IEEE Computer, 25, 3 (March 1992), 63-79. E. HAGERSTEN, A. LANDIN, and S. HARIDI, "DDM--A Cache-Only Memory Architecture", IEEE Computer, 25, 9 (September 1992), 44-54. C. L. SEITZ, "The Cosmic Cube", Comm. ACM (January 1985), 22-33. K. LI and P. HUDAK, "Memory Coherence in Shared Virtual Memory Systems", ACM Trans. on Computer Systems, 7, 4 (November 1989), 321-359. CHAPTER 10 - Recent Implementations and Future ProspectsD. ALPERT, D. AVNON, "Architecture of the Pentium Microprocessor", IEEE Micro, June '93, 11-21. D. PAPWORTH, "Tuning the Pentium Pro MicroArchitecture", IEEE Micro April '96, 8-15. M. SLATER, "The Microprocessor Today", IEEE Micro Dec '96, 32-44. A. YU, "The Future of Microprocessors", IEEE Micro Dec '96, 46-53.
- No. of pages: 650
- Language: English
- Edition: 1
- Published: September 9, 1999
- Imprint: Morgan Kaufmann
- Paperback ISBN: 9781558605398
- eBook ISBN: 9780080573649
MH
Mark D. Hill
Mark D. Hill is Professor and Romnes Fellow in the Computer Sciences and Electrical and Computer Engineering departments at the University of Wisconsin-Madison. His research targets the memory systems of shared-memory multiprocessors and high-performance uniprocessors. Much of his recent work was part of the Wisconsin Wind Tunnel project, which examined supporting multiple parallel programming models on hardware ranging from tightly-coupled multiprocessors to clusters of workstations.
NJ
Norman P. Jouppi
Norman P. Jouppi is Consulting Engineer at Compaq Computer Corporation’s Western Research Laboratory (WRL). Formerly a consulting associate professor in the Department of Electrical Engineering at Stanford University, he has been a key contributor to the architecture and implementation of advanced graphics accelerators (including Neon), the MultiTitan and BIPS microprocessors at WRL, and the MIPS Stanford microprocessor.
GS
Gurindar S. Sohi
Gurindar S. Sohi, a Professor in the Computer Sciences and Electrical and Computer Engineering departments of the University of Wisconsin-Madison, was awarded the 1999 ACM SIGARCH Maurice Wilkes award for contributions in the areas of high issue rate processors and instruction level parallelism. His research has focused on architectural and microarchitectural techniques for high-performance microprocessors.