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PowerPC Microprocessor Common Hardware Reference Platform
A System Architecture
- 1st Edition - June 25, 2012
- Authors: Apple Computer, Inc., International Business Machines, Inc., Motorola Corp.
- Language: English
- eBook ISBN:9 7 8 - 0 - 1 2 - 8 0 1 5 5 5 - 1
This book defines the architecture requirements and minimum system requirementsfor a computer system that is designed to become an open industry standard.These requirements pr… Read more
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Request a sales quoteThis book defines the architecture requirements and minimum system requirementsfor a computer system that is designed to become an open industry standard.These requirements provide a description of the devices, interfaces, and dataformats required to design and build a PowerPC-based computer. This standard isdesigned to provide software compatibility for several operating environments.Systems built to these requirements can use industry-standard componentscurrently found in IBM-compatible and Apple® Macintosh® personal computers. Thesesystems are expected to run various future versions of operating systemsincluding Apple Mac OS™, IBM AIX™ and PowerPC™ Editions of IBM OS/2 Warp Connect™,Microsoft Windows NT™ Workstation, Novell Netware™, and SunSoft Solaris™.
This book is the primary source of information for anyone developing a hardwareplatform, an operating system, or hardware component to be part of thesestandard systems. It describes the hardware-to-operating-system interface thatis essential to anyone building hardware platforms and provides the minimumsystem configurations that platform designers must meet when building a standardplatform. Component manufacturers require this information to producecompatible chips and adapters to use on these platforms, and software developersrequire the information on mandatory functions and documented interfaces.
The architecture is intended to support a range of PowerPC microprocessor-based system implementations including portable, desktop, and server classsystems, and allows multiple operating-system implementations across a widerange of environments and functions. This enables new hardware and softwareenhancements that are necessary for the development of improved userinterfaces, higher performance, and broader operating environments.
PowerPC™ Microprocessor Common Hardware Reference Platform: A System Architectureby IBM Inc & Motorola
- ForewordList of FiguresList of Tables
- About this DocumentGoals of the SpecificationAudience for this DocumentOrganization of this DocumentSuggested ReadingConventions Used in this DocumentAcknowledgmentsComments on this Document
- 1.1 Platform topology
- 2.1 System Operation
- 2.1.1 Control Flow2.1.2 POST2.1.3 Boot Phase2.1.4 Transfer Phase2.1.5 Run-Time2.1.6 Termination
- 2.5.1 Table Description
- 3.1 Address Areas3.2 Address Decoding and Translation
- 3.2.1 Peripheral I/O Address Translation3.2.2 Translation of 32-Bit DMA Addresses in 64-Bit Addressing Systems
- 4.1 Processor Architecture
- 4.1.1 Processor Architecture Compliance4.1.2 PowerPC Microprocessor Differences4.1.3 Processor Interface Variations4.1.4 PowerPC Architecture Features Deserving Comment
- 4.2.1 System Memory4.2.2 Storage Ordering Models4.2.3 Memory Controllers4.2.4 Cache Memory
- 5.1 PCI Host Bridge (PHB) Architecture
- 5.1.1 PHB Implementation Options5.1.2 Data Buffering and Instruction Queuing5.1.3 Byte Ordering Conventions5.1.4 PCI Bus Protocols5.1.5 Programming Model
- 5.2.1 What Must Talk to What5.2.2 PCI to PCI Bridges5.2.3 PCI to ISA Bridges5.2.4 16-Bit PC Card (PCMCIA) and Cardbus PC Card Bridges
- 6.1 Interrupt Controller Architecture6.2 Distributed Implementation - A Proposal
- 7.1 RTAS Introduction7.2 RTAS Environment
- 7.2.1 Machine State7.2.2 Register Usage7.2.3 RTAS Critical Regions7.2.4 Resource Allocation and Use7.2.5 Instantiating RTAS7.2.6 RTAS Device Tree Properties7.2.7 Calling Mechanism and Conventions7.2.8 Return Codes
- 7.3.1 restart-rtas7.3.2 NVRAM Access Functions7.3.3 Time of Day7.3.4 Error and Event Reporting7.3.5 PCI Configuration Space7.3.6 Operator Interfaces and Platform Control7.3.7 Power Management7.3.8 Suspend and Hibernate7.3.9 Reboot7.3.10 Caches7.3.11 SMP Support
- 8.1 System Requirements8.2 Structure8.3 Signatures8.4 Architected Partitions
- 8.4.1 Open Firmware (0x50)8.4.2 Hardware (0x52)8.4.3 System (0x70)8.4.4 Configuration (0x71)8.4.5 Error Log (0x72)8.4.6 Multi-Boot (0x73)8.4.7 Free Space (0x7F)
- 9.1 PCI Devices
- 9.1.1 Resource Locking9.1.2 PCI Expansion ROMs9.1.3 Assignment of Interrupts to PCI Devices9.1.4 PCI Devices with Required Register Definitions9.1.5 PCI-PCI Bridge Devices9.1.6 Graphics Controller and Monitor Requirements for Clients
- 10.1 Introduction10.2 RTAS Error and Event Classes
- 10.2.1 Internal Error Indications10.2.2 Environmental and Power Warnings10.2.3 Power Management Events
- 10.3.1 Introduction10.3.2 RTAS Error/Event Return Format
- 11.1 Power Management Concepts
- 11.1.1 Power Management Policy Versus Mechanism11.1.2 Device Power States11.1.3 System Power Management States11.1.4 System Power Transitory States11.1.5 Power Domains and Domain Control Points11.1.6 Power Sources11.1.7 Batteries11.1.8 Power Management Events11.1.9 Explicit Transfer of Power Management Policy11.1.10 EPA Energy Star Compliance
- 11.2.1 Definition of Power Management Related Parameters Utilized by RTAS11.2.2 Open Firmware Device Tree Properties11.2.3 General Hardware Requirements
- 11.3.1 General Requirements
- 12.1 SMP System Organization12.2 An SMP Boot Process
- 12.2.1 SMP-Safe Boot12.2.2 Finding the Processor Configuration12.2.3 SMP-Efficient Boot12.2.4 Use of a Service Processor
- C.1 Little-Endian Address and Data TranslationC.2 Conforming Bi-Endian Designs
- C.2.1 Processor and I/O Mode ControlC.2.2 Approach#1-Bi-Endian Memory and Bi-Endian I/O DesignC.2.3 Approach #2-Bi-Endian I/O Design
- No. of pages: 309
- Language: English
- Edition: 1
- Published: June 25, 2012
- Imprint: Morgan Kaufmann
- eBook ISBN: 9780128015551