Network Processors
Architecture, Programming, and Implementation
- 1st Edition - July 16, 2008
- Latest edition
- Author: Ran Giladi
- Language: English
Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires… Read more
Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. This book leads the reader through the requirements and the underlying theory of networks, network processing, and network processors. It covers implementation of network processors and intergrates EZchip Microcode Development Environment so that you can gain hands-on experience in writing high-speed networking applications. By the end of the book, the reader will be able to write and test applications on a simulated network processor.
- Comprehensive, theoretical, and pracitical coverage of networks and high-speed networking applications
- Descirbes contemporary core, metro, and access networks and their processing algorithms
- Covers network processor architectures and programming models, enabling readers to assess the optimal network processor typer and configuration for their application
- Free download from http://www.cse.bgu.ac.il/npbook includes microcode development tools that provide hands-on experience with programming a network processor
PRIMARY- Industry practitioners; systems engineers, architects, product managers and software engineers from communication systems vendors, telecommunications carriers and service providers; application developers and R&D level engineers that need high-speed networking solutions, for example in defense and intelligence communities.
SECONDARY- Text for undergraduate and graduate level courses on Network Processors and on high-speed networking; reference for researchers.
SECONDARY- Text for undergraduate and graduate level courses on Network Processors and on high-speed networking; reference for researchers.
CHAPTER 1 Introduction and Motivation
1.1 Network Processors Ecosystem
1.2 Communication Systems and Applications
1.3 Network Elements
1.4 Network Processors
1.5 Structure of This Book
1.6 Summary
PART 1 Networks
CHAPTER 2 Networking Fundamentals
2.1 Introduction
2.2 Networks Primer
2.3 Data Networking Models
2.4 Basic Network Technologies
2.5 Telecom Networks
2.6 Data Networks
2.7 Summary
Appendix A
Appendix B
CHAPTER 3 Converged Networks
3.1 Introduction
3.2 From Telecom Networks to Data Networks
3.3 From Datacom to Telecom
3.4 Summary
Appendix A
CHAPTER 4 Access and Home Networks
4.1 Access Networks
4.2 Home and Building Networks
4.3 Summary
PART 2 Processing
CHAPTER 5 Packet Processing
5.1 Introduction and Definitions
5.2 Ingress and Egress
5.3 Framing
5.4 Parsing and Classification
5.5 Search, Lookup, and Forwarding
5.6 Modification
5.7 Compression and Encryption
5.8 Queueing and Traffic Management
5.9 Summary
CHAPTER 6 Packet Flow Handling
6.1 Definitions
6.2 Quality of Service
6.3 Class of Service
6.4 QoS Mechanisms
6.5 Summary
CHAPTER 7 Architecture
7.1 Introduction
7.2 Background and Definitions
7.3 Equipment Design Alternatives: ASICs versus NP
7.4 Network Processors Basic Architectures
7.5 Instruction Set (Scalability; Processing Speed)
7.6 NP Components
7.7 Summary
CHAPTER 8 Software
8.1 Introduction
8.2 Conventional Systems
8.3 Programming Models Classification
8.4 Parallel Programming
8.5 Pipelining
8.6 Network Processor Programming
8.7 Summary
Appendix A
Appendix B
Appendix C
CHAPTER 9 NP Peripherals
9.1 Switch Fabrics
9.2 CoProcessors
9.3 Summary
PART 3 A Network Processor: EZchip
CHAPTER 10 EZchip Architecture, Capabilities, and Applications
10.1 General description
10.2 System Architecture
10.3 Lookup Structures
10.4 Counters, Statistics and Rate Control
10.5 Traffic Management
10.6 Stateful Classification
10.7 Multicast Frames
10.8 Data Flow
10.9 Summary
CHAPTER 11 EZchip Programming
11.1 Instruction Pipeline
11.2 Writing NP Microcode
11.3 Preprocessor Overview
11.4 Developing and Running NP Applications
11.5 TOP Common Commands
11.6 Summary
Appendix A
CHAPTER 12 Parsing
12.1 Internal Engine Diagram
12.2 TOPparse Registers
12.3 TOPparse Structures
12.4 TOPparse Instruction Set
12.5 Example
12.6 Summary
Appendix A
Appendix B
Appendix C
CHAPTER 13 Searching
13.1 Introduction
13.2 Internal Engine Diagram
13.3 TOPsearch I Structures
13.4 Interface to TOPparse (Input to TOPsearch)
13.5 Interface to TOPresolve (Output of TOPsearch)
13.6 Hash Table Learning
13.7 Example
13.8 Summary
CHAPTER 14 Resolving
14.1 Internal Engine Diagram
14.2 TOPresolve Registers
14.3 TOPresolve Structures
14.4 TOPresolve Instruction Set
14.5 Example
14.6 Summary
Appendix A
Appendix B
Appendix C
CHAPTER 15 Modifying
15.1 Introduction
15.2 Internal Engine Diagram
15.3 TOPmodify Registers
15.4 TOPmodify Structures
15.5 TOPmodify Instruction Set
15.6 Example
15.7 Summary
Appendix A
Appendix B
Appendix C
CHAPTER 16 Running the Virtual Local Area Network Example
16.1 Installation
16.2 Getting Started
16.3 Microcode Development Workflow
16.4 Summary
CHAPTER 17 Writing Your First High-Speed Network Application
17.1 Introduction
17.2 Data Flow and TOP Microcode
17.3 Data Structures
17.4 Summary
List of Acronyms
- Edition: 1
- Latest edition
- Published: July 16, 2008
- Language: English
RG
Ran Giladi
Ran Giladi is an associate professor in the department of Communication Systems Engineering at Ben-Gurion University of the Negev, Beer Sheva; he founded the department and has headed it for several years. In addition, he has taught in the Electrical Engineering Department and the Business School at Tel-Aviv University. Dr. Giladi has also been a system programmer, an R&D manager, a VP of R&D, and founder and CEO of several data communication companies. He is involved in the Israeli high-tech industry, serves as a board member in several companies (among them EZchip Technologies, a leading vendor of network processors), and is currently a venture partner with DFJ-TFV. His research interests include computer and communications systems performance, data and telecom networks, and network management systems. Dr. Giladi received a B.A. in physics, an M.Sc. in biomedical engineering from the Technion, and a Ph.D. in information systems from Tel-Aviv University.
Affiliations and expertise
Associate Professor, Ben-Gurion University, Israel.