Handbook of Thin Film Deposition

Theory, Technology and Semiconductor Applications

5th Edition - October 8, 2024
Editors: Dominic Schepis, Krishna Seshan
Language: English
Paperback ISBN:
9 7 8 - 0 - 4 4 3 - 1 3 5 2 3 - 1
eBook ISBN:
9 7 8 - 0 - 4 4 3 - 1 3 5 2 4 - 8

Handbook of Thin Film Deposition: Theory, Technology and Semiconductor Applications, Fifth Edition, is a comprehensive reference focusing on thin film technologies and applicati… Read more

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Handbook of Thin Film Deposition: Theory, Technology and Semiconductor Applications, Fifth Edition, is a comprehensive reference focusing on thin film technologies and applications used in the semiconductor industry and the closely related areas of thin film deposition, thin film microproperties, ferroelectric films, LED research, and materials for memory applications, and other thin film applications.

Of particular note in this new edition is the coverage of “reduction to practice,” a phase where the idea for a technology transitions from a concept to actual implementation. This section includes chapters that review the most relevant methods to fabricate thin films toward practical applications. This book also discusses the latest applications of various thin film deposition technologies.

Handbook of Thin Film Deposition: Theory, Technology and Semiconductor Applications, Fifth Edition, is suitable for students, materials scientists, engineers, and managers working in academia or semiconductor-related R&D.

Title of Book
Cover image
Title page
Table of Contents
Copyright
Dedication
Contributors
Foreword
Preface
Acknowledgments
Part I. Introduction
Chapter 1. The role of thin films in nanotechnology
1 Introduction
2 Device scaling becomes the driver
2.1 Device roadmaps (Fig. 1.1)
2.2 Thin film characterization
3 Thin film challenges
4 Handbook organization
Supplementary materials
Part II. Reduction to practice
Chapter 2. Process integration for on-chip interconnects
1 Introduction
2 Device scaling
3 Copper interconnect processing
3.1 Process flow
3.2 Low-k dielectrics
3.3 Dielectric patterning
3.4 Metallization
3.5 Chemical mechanical polishing (CMP)
4 Reliability
4.1 Electromigration
4.2 Stress-induced voiding
4.3 Time-dependent dielectric breakdown (TDDB)
4.4 Package reliability
5 Future directions
Chapter 3. Sputter processing
1 Introduction
2 Energy and kinematics of sputtered atoms
3 Energy dependence of sputtering
3.1 Cosine sputtering law
4 Plasmas and sputtering systems
4.1 DC diode plasmas
4.2 RF plasmas
4.3 Magnetron sputtering
4.3.1 Magnetron designs
5 Reactive sputter deposition
5.1 Current–voltage hysteresis in reactive sputtering systems
6 Sputter-tool design and applications for semiconductor technology
6.1 Batch/planetary systems
6.2 Single-wafer systems
6.2.1 Clustered sputter-tool layout
6.3 Directional sputter deposition
6.3.1 Collimation
6.4 Current applications: Nanometer-scale engineering using PVD
6.4.1 PVD copper-alloy seedlayers for self-capping layers for Cu interconnects
6.4.2 PVD copper fill of advanced-groundrule interconnects using reflow
6.4.3 Via-resistance reduction using selective ALD barrier sequences
7 Contamination and metrology
7.1 Metrology of sputtered films
7.1.1 Resistance/four-point probe measurement
7.1.2 Non-destructive thickness measurements
7.2 Contamination control and prevention in sputtering systems
7.2.1 Tooling and shielding considerations
7.2.2 Extrinsic contamination control: RGA monitoring
8 Future directions
Chapter 4. Epitaxial growth processes for high performance advanced CMOS devices
1 Introduction
1.1 MOSFET device scaling
2 Strained Si technology with epitaxial process
2.1 Mobility enhancement technology
2.2 New device structure with three-dimensional structure
3 Strain engineering for nanoscale strained SiGe FinFET
3.1 Strain engineering for SiGe FinFET
3.1.1 Comparative study of strain and Ge content in Si1-xGex channel
3.2 Local strain in nanoscale SiGe FinFET
3.2.1 Quantification of local strain distributions in nanoscale strained SiGe FinFET structures
3.2.2 Local layout effect (LLE) in strained SiGe channel pFinFET and LLE mitigation
4 Advanced source drain extension formation for scalded devices
4.1 Dopant diffusion control for device junction formation
4.2 Advanced epitaxial growth technique for source drain extension formation in scaled FinFET devices
4.2.1 Si:As SDE formation on FinFET device
4.2.2 Electrical sensitivities to SDE material and lateral recess for device performance
5 Performance enhancement techniques for gate-all-around (GAA) pFET device
5.1 Highly compressive strained SiGe channel application for GAA NS pFET
5.1.1 SiGe cladded nanosheet structure formation
5.1.2 Effect of Ge fraction and SiGe thickness on device characteristics
5.2 (110) versus (001) channel orientation GAA NS technology
5.2.1 Stacked Si NS pFET and nFET devices fabrication on (001) and (110) bulk Si substrates
5.2.2 Electrical sensitivities to TSi for device performance
6 Conclusions
Chapter 5. Equipment and manufacturability issues in chemical vapor deposition processes
1 Introduction
2 Basic principles of CVD
3 A brief history of CVD equipment
4 CVD applications and their impact on scaling
4.1 CVD metals
4.2 Metals more commonly deposited by non-CVD equipment
4.3 Dielectrics
4.4 Semiconductors
5 Contamination and metrology
5.1 Contamination
5.2 Metrology
5.2.1 Sample imaging and film thickness: atomic force microscopy, Nomarski, transmission electron microscopy, scanning electron microscopy, and optical microscopy
5.2.2 Composition: XRD, secondary mass spectrometry, mass spectroscopy, and Fourier transform infrared
5.2.3 Mechanical: stud pull, wafer bowing, and nanoindentation
5.2.4 Electrical: hall, reciprocal space mapping, and capacitance–voltage dot measurement
6 Summary of CVD technologies
6.1 ALD
6.2 Subatmospheric ACVD
6.3 LPCVD
6.4 APCVD
6.5 MOCVD
6.6 PECVD
7 CVD tool selection for research and manufacturing
8 CVD trends and projection
Chapter 6. CMP: Scaling down and stacking up: How the trends in semiconductors are affecting chemical-mechanical planarization
1 Introduction
2 CMP challenges
2.1 More CMP steps
2.2 Sub-nm wafer-level uniformity
2.3 Planarity and surface roughness
2.4 Even lower tolerance for defectivity
2.5 Post CMP metal loss in fine patterns
3 The path forward
3.1 Equipment
3.2 Slurry
3.3 Pads and conditioners
3.3.1 Pads with engineered asperities (EA pads)
3.3.2 Post CMP clean
4 Conclusions
Chapter 7. Limits of gate dielectrics scaling
1 Introduction
2 Dennard scaling theory
2.1 Constant electric-field scaling
2.2 Generalized scaling
3 Gate oxide and EOT scaling
3.1 Physical structure of hafnium dioxide
4 Hafnium based ternary, quaternary and bilayer oxides for EOT scaling
4.1 Hafnium oxynitride (HfOxN)
4.2 Hafnium lanthanum oxynitride (HfLaOxN)
4.3 Bilayer gate dielectrics: HfO2/TiO2 higher ‘K” for EOT scaling
5 EOT scaling through interfacial layer
5.1 Nitrided interfacial layer (SiON)
5.2 Interfacial layer scavenging
6 Ab-initio modeling
6.1 Tool to evaluate higher K dielectric
6.2 Effective work function engineering
7 Gate oxides in FinFET era
8 High voltage (HV) input/output (I/O) gate oxides with HiK/MG for advanced SOC (FinFET and FDSOI)
9 SiGe as a pFET channel (cSiGe) to enable gate oxide scaling
10 Nano-sheet (NS) gate-all-around (GAA) transistor technology and its implication on gate-oxide for logic and I/O transistors
10.1 FinFET versus nano-sheet gate-all-around structure comparison
10.2 Brief review of nano-sheet transistor structure process integration
10.3 Logic transistor interfacial layer and gate oxide challenges for nano-sheet devices
10.4 Nano-sheet high voltage I/O transistor gate dielectrics and their Co-integration with logic transistor
11 Si/SiGe heterostructure-based I/O devices with low temperature ALD oxide and densification
11.1 Integrate with nano-sheet gate-all-around device
11.2 Heterostructure device structure results
11.3 Electrical results and discussions
11.4 Gate stack characteristics
12 High mobility (high atomic % Ge, SiGe) channel: Logic IL and I/O gate oxide research results
13 Conclusion
Part III. Applications and limitations
Chapter 8. Semiconductor reliability overview
1 Introduction
2 Definition of reliability
3 Semiconductor reliability balancing act
4 Challenges and principal degradation mechanisms in semiconductor reliability
5 Front end of line reliability, back end of line reliability, and middle of the line reliability
6 Reliability assessment methodologies
7 Mitigation strategies
8 Test structures and methodologies for reliability assessment
9 Conclusion
Chapter 9. Thin film development for LED technologies
1 Introduction
2 Development of green-emitting hexagonal InGaN/GaN LEDs
3 State-of-the art of bulk cubic GaN and InGaN/GaN LEDs
4 Computation-based design of cubic InGaN/GaN LED
5 Experimental growth of cubic GaN on U-grooved Si (100) for green LEDs
6 Future work
Chapter 10. Emerging ferroelectric thin films: Applications and processing
1 Introduction
2 History
3 Principle
3.1 Ferroelectric models
4 Thin films
5 Thin film deposition processes
5.1 Chemical solution deposition (CSD)
5.2 Sputter deposition
5.3 Pulsed laser deposition
5.4 Atomic layer deposition (ALD)
5.5 Molecular beam epitaxy (MBE)
5.6 Metal-organic chemical vapor deposition (MOCVD)
6 Patterning of ferroelectric thin films
7 Characterization of ferroelectric films
7.1 Hysteresis P-E loop
7.2 Piezoresponse force microscopy (PFM)
7.3 The corona-Kelvin technique
7.4 Other ultrathin advanced techniques
8 Ferroelectric thin film applications
8.1 Ferroelectric devices
8.1.1 Variable capacitors: metal ferroelectric metal (MFM), metal ferroelectric semiconductor (MFS)
8.1.2 Ferroelectric tunnel junctions: FTJ
8.2 In-memory and neuromorphic computing
8.3 Pyroelectric, piezoelectric and energy harvesting
8.4 Tunable microwave devices
9 Three exemplary ferroelectric films
9.1 Hafnium oxide based ferroelectric films
9.2 Barium–strontium–titanate (BST)
9.3 Aluminum scandium nitride (AlScN)
10 Reliability of ferroelectric films
10.1 Wake-up
10.2 Fatigue
10.3 Field cycling endurance
10.4 Retention
10.5 Imprint effect
10.6 Scaling
11 Conclusions
Chapter 11. Thin films in semiconductor memory
1 Introduction
2 DRAM
2.1 Access transistor
2.2 DRAM capacitor
2.3 Future DRAM cells
3 NAND
3.1 NAND transistor
3.2 ONO storage layers
4 Other semiconductor memories
4.1 3D XPoint memory
4.2 Ferroelectric memory
5 Conclusion
Chapter 12. Yield impact of defects from thin films and other processing steps
1 Introduction
2 Examples of different fail modes
3 Defect density and its impact on yield
4 Various yield assessment structures
5 SRAM yield learning methodology
6 How to cheat defect density by adding redundency
7 Conclusion
Summary
Index

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Handbook of Thin Film Deposition

Theory, Technology and Semiconductor Applications

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Dominic Schepis

Krishna Seshan