Formal Verification
An Essential Toolkit for Modern VLSI Design
- 2nd Edition - May 26, 2023
- Imprint: Morgan Kaufmann
- Authors: Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar
- Language: English
- Paperback ISBN:9 7 8 - 0 - 3 2 3 - 9 5 6 1 2 - 3
- eBook ISBN:9 7 8 - 0 - 3 2 3 - 9 5 6 1 3 - 0
Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working e… Read more
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Request a sales quoteFormal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.
Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.
- Covers formal verification algorithms that help users gain full coverage without exhaustive simulation
- Helps readers understand formal verification tools and how they differ from simulation tools
- Shows how to create instant testbenches to gain insights into how models work and to find initial bugs
- Presents insights from Intel insiders who share their hard-won knowledge and solutions to complex design problems
Professional engineers involved in chip design or verification
- Cover image
- Title page
- Table of Contents
- Copyright
- Foreword by Harry Foster
- Foreword to 1st edition by Robert Bentley
- Acknowledgments
- Chapter 1. Formal verification: from dreams to reality
- What is FV?
- Why this book?
- A motivating anecdote
- FV: the next level of depth
- The emergence of practical FV
- Challenges in implementing FV
- Amplifying the power of formal
- Getting the most out of this book
- Chapter 2. Basic formal verification algorithms
- Formal verification in the validation process
- A simple vending machine example
- Comparing models
- Cones of influence
- Formalizing operation definitions
- Boolean algebra notation
- Binary decision diagrams
- Boolean satisfiability
- Chapter summary
- Chapter 3. Introduction to SystemVerilog Assertions
- Basic assertion concepts
- Sequences, properties, and concurrent assertions
- Summary
- Practical tips from this chapter
- Chapter 4. Formal property verification
- What is FPV?
- Example for this chapter: combination lock
- Bringing up a basic FPV environment
- How is FPV different from simulation?
- Deciding where and how to run FPV
- Summary
- Practical tips from this chapter
- Chapter 5. Effective formal property verification for design exercise
- Example for this chapter: traffic light controller
- Creating a design exercise plan
- Setting up the design exercise FPV environment
- Wiggling the design
- Exploring more interesting behaviors
- Removing simplifications and exploring more behaviors
- Summary
- Chapter 6. Effective FPV for verification
- Deciding on your FPV goals
- Staging your FPV efforts
- Example for this chapter: simple ALU
- Understanding the design
- Creating the FPV verification plan
- Removing simplifications and exploring more behaviors
- Summary
- Chapter 7. Formal property verification apps for specific problems
- Reusable protocol verification
- Unreachable coverage elimination
- Connectivity verification
- Control register verification
- Postsilicon debug and reactive FPV
- Summary
- Chapter 8. Formal equivalence verification
- Types of equivalence to check
- FEV use cases
- Running FEV
- Additional FEV challenges
- Summary
- Chapter 9. Formal verification's greatest bloopers: the danger of false positives
- Misuse of the SVA language
- Vacuity issues
- Implicit or unstated assumptions
- Division of labor
- Summary
- Practical tips from this chapter
- Chapter 10. Dealing with complexity
- Design state and associated complexity
- Example for this chapter: memory controller
- Observing complexity issues
- Simple techniques for convergence
- Helper assumptions … and not-so-helpful assumptions
- Generalizing analysis using free variables
- Abstraction models for complexity reduction
- Semiformal verification
- Evading the complexity problem: design and verification working together
- Summary
- Chapter 11. Formal signoff on real projects
- Overall signoff methodology
- Plan and architect
- Apply and execute
- Cover and regress
- Track and close
- Conclusions
- Practical tips from this chapter
- Chapter 12. Your new FV-aware lifestyle
- Uses of FV
- Individual preparation to use FV
- Getting a team started on FV
- Making your manager happy
- What do FVers really do?
- Summary
- Practical tips from this chapter
- Index
- Edition: 2
- Published: May 26, 2023
- No. of pages (Paperback): 424
- No. of pages (eBook): 424
- Imprint: Morgan Kaufmann
- Language: English
- Paperback ISBN: 9780323956123
- eBook ISBN: 9780323956130
ES
Erik Seligman
Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation” podcast, and has served as an elected director on the Hillsboro school board.
Affiliations and expertise
Senior Product Engineering Architect, Cadence Design SystemsTS
Tom Schubert
Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.
Affiliations and expertise
Adjunct Professor, Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USAMK
M V Achutha Kiran Kumar
M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'.
Affiliations and expertise
Intel Corporation, Bengaluru, Karnataka, IndiaRead Formal Verification on ScienceDirect