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BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage
- 1st Edition - April 26, 2023
- Authors: Chenming Hu, Harshit Agarwal, Chetan Gupta, Yogesh Singh Chauhan
- Language: English
- Paperback ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 7 7 - 5
- eBook ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 7 8 - 2
BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss t… Read more
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Request a sales quoteBSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss the fundamental core of the model, but also provide details of the recent developments and new real-device effect models. In addition, the book covers the parameter extraction procedures, addressing geometrical scaling, temperatures, and more. There is also a dedicated chapter on extensive quality testing procedures and experimental results. This book discusses every aspect of the model in detail, and hence will be of significant use for the industry and academia.
Those working in the semiconductor industry often run into a variety of problems like model non-convergence or non-physical simulation results. This is largely due to a limited understanding of the internal operations of the model as literature and technical manuals are insufficient. This also creates huge difficulty in developing their own IP models. Similarly, circuit designers and researcher across the globe need to know new features available to them so that the circuits can be more efficiently designed.
- Reviews the latest advances in fabrication methods for metal chalcogenide-based biosensors
- Discusses the parameters of biosensor devices to aid in materials selection
- Provides readers with a look at the chemical and physical properties of reactive metals, noble metals, transition metals chalcogenides and their connection to biosensor device performance
Materials Scientists and Engineers; Electrical Engineers
- Cover image
- Title page
- Table of Contents
- Copyright
- Chapter 1: Compact Models and the Road Leading to BSIM-BULK
- Abstract
- 1.1. Circuit simulation and compact models
- 1.2. The beginnings of BSIM and industry-standard compact model
- 1.3. BSIM-BULK
- 1.4. Summary
- References
- Chapter 2: BSIM-BULK Core Model
- Abstract
- 2.1. Basic formulation
- 2.2. Inversion charge linearization and pinch-off potential
- 2.3. Normalized charge density
- 2.4. Drain current model
- 2.5. Comparison of BSIM4 and BSIM-BULK models
- References
- Chapter 3: BSIM-BULK Real Device Effect Models
- Abstract
- 3.1. Analytical modeling of bulk charge effect
- 3.2. Enumeration of various real device effects in threshold voltage
- 3.3. Vertical-field mobility degradation
- 3.4. Drain saturation voltage
- 3.5. Output conductance
- 3.6. Sub-threshold hump model
- 3.7. Series resistance model
- 3.8. Impact of strong halo implants on current and transconductance
- References
- Chapter 4: Leakage Current
- Abstract
- 4.1. Introduction
- 4.2. Weak-inversion current
- 4.3. Modeling of bulk current
- 4.4. Gate tunneling current model
- References
- Chapter 5: BSIM-BULK Charge and Capacitance Model
- Abstract
- 5.1. Charge model
- 5.2. Quantum mechanical effect (QME)
- 5.3. Parasitic capacitance model
- Appendix 5.A. Bulk charge with poly-depletion effect
- References
- Chapter 6: Noise and RF Modeling
- Abstract
- 6.1. Introduction
- 6.2. Channel and gate thermal noise
- 6.3. Series resistance thermal noise
- 6.4. Gate current shot noise
- 6.5. Flicker noise
- 6.6. BSIM-BULK RF models
- 6.7. BSIM-BULK small signal model
- 6.8. Modeling of the gate resistance
- 6.9. Modeling of the substrate network
- References
- Chapter 7: Junction Diode and Layout Dependent Parasitic Model
- Abstract
- 7.1. Basic formulation
- 7.2. Asymmetric MOS junction diode models
- 7.3. Layout-dependent parasitics models
- References
- Chapter 8: Compact Modeling of High Voltage Transistors
- Abstract
- 8.1. Introduction
- 8.2. Drift region resistance modeling
- 8.3. Drift region charge model
- 8.4. Model results and validation
- References
- Chapter 9: Self-Heating and Thermal Effects
- Abstract
- 9.1. Basic formulation
- 9.2. Temperature dependence of band-gap and intrinsic carrier concentration
- 9.3. Temperature dependence of subthreshold characteristics
- 9.4. Temperature dependence of the linear-region characteristics
- 9.5. Temperature dependence of saturation characteristics
- 9.6. Temperature dependence of junction diode IV
- 9.7. Temperature dependence of junction diode CV
- 9.8. Self-heating effect
- Chapter 10: Parameter Extraction
- Abstract
- 10.1. Parameter extraction methodology
- 10.2. Extraction of main physical effects & geometry
- 10.3. Extraction of short channel effects & length scaling parameters
- 10.4. Extraction of narrow channel effects & width scaling parameters
- 10.5. Extraction of parameters for narrow/short channel devices
- 10.6. Extraction of temperature dependence parameters
- 10.7. Model validation results
- 10.8. Corner modeling
- References
- Chapter 11: BSIM-BULK Benchmark Tests
- Abstract
- 11.1. Introduction
- 11.2. DC tests
- 11.3. Symmetry test
- 11.4. Harmonic balance test
- 11.5. Capacitance reciprocity test
- References
- Index
- No. of pages: 270
- Language: English
- Edition: 1
- Published: April 26, 2023
- Imprint: Woodhead Publishing
- Paperback ISBN: 9780323856775
- eBook ISBN: 9780323856782
CH
Chenming Hu
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California, Berkeley. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica.He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching - the Berkeley Distinguished Teaching Award.
Affiliations and expertise
Professor Emeritus, University of California, Berkeley, CA, USAHA
Harshit Agarwal
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization.
Affiliations and expertise
Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USACG
Chetan Gupta
He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization.
Affiliations and expertise
Principal Engineer, Micron Technologies, IndiaYC
Yogesh Singh Chauhan
Yogesh Singh Chauhan is a Chair professor in the department of electrical engineering at Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices. He is the Fellow of IEEE and Indian National Academy of Engineering. He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the chairperson of IEEE U.P. section and IEEE-EDS Compact Modeling Committee. He has published more than 400 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.
Affiliations and expertise
Chair Professor, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India