BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage
- 1st Edition - April 26, 2023
- Imprint: Woodhead Publishing
- Authors: Chenming Hu, Harshit Agarwal, Chetan Gupta, Yogesh Singh Chauhan
- Language: English
- Paperback ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 7 7 - 5
- eBook ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 7 8 - 2
BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss t… Read more
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Request a sales quoteBSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss the fundamental core of the model, but also provide details of the recent developments and new real-device effect models. In addition, the book covers the parameter extraction procedures, addressing geometrical scaling, temperatures, and more. There is also a dedicated chapter on extensive quality testing procedures and experimental results. This book discusses every aspect of the model in detail, and hence will be of significant use for the industry and academia.
Those working in the semiconductor industry often run into a variety of problems like model non-convergence or non-physical simulation results. This is largely due to a limited understanding of the internal operations of the model as literature and technical manuals are insufficient. This also creates huge difficulty in developing their own IP models. Similarly, circuit designers and researcher across the globe need to know new features available to them so that the circuits can be more efficiently designed.
- Reviews the latest advances in fabrication methods for metal chalcogenide-based biosensors
- Discusses the parameters of biosensor devices to aid in materials selection
- Provides readers with a look at the chemical and physical properties of reactive metals, noble metals, transition metals chalcogenides and their connection to biosensor device performance
Materials Scientists and Engineers; Electrical Engineers
I. Background
1. Introduction
2. BSIM4: Strength and Missing Pieces
3. Concept of BSIM-BULK Model
4. New Features in BSIM-BULK Model
II. BSIM-BULK Core Model
1. Introduction
2. Core model formulation and approximations
3. Numerical Techniques for Analytical Solution
4. Core Drain Current and Charge Model
5. Core Model Equivalence with BSIM4 Model
III. Real Device Effects
1. Introduction
2. Modeling Bulk Charge Effect
a. Impact of Doping Profile
b. Body Bias Dependence
3. Carrier Transport
a. Universal Mobility, Velocity Saturation and Overshoot
b. Ballistic transport
4. Channel-length modulation
5. Drain-Induced barrier lowering effect
6. Quantum Mechanical Effect
7. Sub-threshold Hump Model
8. Series resistance
9. Impact of Halo Implants on Current and Transconductance
10. Output Conductance Model
11. Narrow Width Effects
IV. Leakage current and thermal effects
1. Gate Current Model
2. Gate-induced Drain Leakage Model (GIDL)
3. Thermal Effects and Self-Heating Effect Model
4. Sub-Surface Leakage
V. BSIM-BULK Charge and Capacitance Model
1. Intrinsic charge model with fast core model
2. Impact of back-gate on capacitances
3. Extrinsic capacitance model
a. Overlap capacitance
b. Fringe capacitances
VI. Noise and RF Modeling
1. Flicker Noise
a. Flicker Noise Modeling
b. Flicker Noise in Advanced Nodes
2. Thermal Noise
3. Shot Noise
4. Gate Resistance Network
5. Non-Quasi Static Effect
6. Substrate Resistance Network
VII. Complete RF Model
7. Junction Diode and Layout Dependent Parasitic Model
1. Introduction
2. Junction Diode IV Model
3. Junction Diode CV Model
4. Layout Dependent Source/Drain Resistance Model
VIII. Compact Modeling of High Voltage Devices
1. Introduction
2. Drift Region Resistance Modeling
3. Drift Region Charge Model
4. Model Activation and Validation
IX. Parameter Extraction
1. Introduction
2. Parameter Extraction Methodology
3. Extraction of Large Sized Device Parameters
4. Short Channel Device Parameters and Geometrical Scaling
5. Extraction of Temperature Dependent Parameters
6. Conclusion
X. BSIM-BULK Model Quality Testing
1. Introduction
2. Symmetry Tests for AC and DC
3. Weak and Strong Inversion Tests
4. Reciprocity test for capacitances
5. Test for self-heating effect model
6. Test for thermal noise
1. Introduction
2. BSIM4: Strength and Missing Pieces
3. Concept of BSIM-BULK Model
4. New Features in BSIM-BULK Model
II. BSIM-BULK Core Model
1. Introduction
2. Core model formulation and approximations
3. Numerical Techniques for Analytical Solution
4. Core Drain Current and Charge Model
5. Core Model Equivalence with BSIM4 Model
III. Real Device Effects
1. Introduction
2. Modeling Bulk Charge Effect
a. Impact of Doping Profile
b. Body Bias Dependence
3. Carrier Transport
a. Universal Mobility, Velocity Saturation and Overshoot
b. Ballistic transport
4. Channel-length modulation
5. Drain-Induced barrier lowering effect
6. Quantum Mechanical Effect
7. Sub-threshold Hump Model
8. Series resistance
9. Impact of Halo Implants on Current and Transconductance
10. Output Conductance Model
11. Narrow Width Effects
IV. Leakage current and thermal effects
1. Gate Current Model
2. Gate-induced Drain Leakage Model (GIDL)
3. Thermal Effects and Self-Heating Effect Model
4. Sub-Surface Leakage
V. BSIM-BULK Charge and Capacitance Model
1. Intrinsic charge model with fast core model
2. Impact of back-gate on capacitances
3. Extrinsic capacitance model
a. Overlap capacitance
b. Fringe capacitances
VI. Noise and RF Modeling
1. Flicker Noise
a. Flicker Noise Modeling
b. Flicker Noise in Advanced Nodes
2. Thermal Noise
3. Shot Noise
4. Gate Resistance Network
5. Non-Quasi Static Effect
6. Substrate Resistance Network
VII. Complete RF Model
7. Junction Diode and Layout Dependent Parasitic Model
1. Introduction
2. Junction Diode IV Model
3. Junction Diode CV Model
4. Layout Dependent Source/Drain Resistance Model
VIII. Compact Modeling of High Voltage Devices
1. Introduction
2. Drift Region Resistance Modeling
3. Drift Region Charge Model
4. Model Activation and Validation
IX. Parameter Extraction
1. Introduction
2. Parameter Extraction Methodology
3. Extraction of Large Sized Device Parameters
4. Short Channel Device Parameters and Geometrical Scaling
5. Extraction of Temperature Dependent Parameters
6. Conclusion
X. BSIM-BULK Model Quality Testing
1. Introduction
2. Symmetry Tests for AC and DC
3. Weak and Strong Inversion Tests
4. Reciprocity test for capacitances
5. Test for self-heating effect model
6. Test for thermal noise
- Edition: 1
- Published: April 26, 2023
- No. of pages (Paperback): 270
- Imprint: Woodhead Publishing
- Language: English
- Paperback ISBN: 9780323856775
- eBook ISBN: 9780323856782
CH
Chenming Hu
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching – the Berkeley Distinguished Teaching Award.
Affiliations and expertise
TSMC Distinguished Chair Professor Emeritus, University of California Berkeley, USAHA
Harshit Agarwal
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization.
Affiliations and expertise
Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USACG
Chetan Gupta
He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization.
Affiliations and expertise
Principal Engineer, Micron Technologies, IndiaYC
Yogesh Singh Chauhan
Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Affiliations and expertise
Chair Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, IndiaRead BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage on ScienceDirect