Ferroelectrics and Negative Capacitance

Girish Pahwa is an assistant professor at the International College of Semiconductor Technology at National Yang Ming Chiao Tung University. Girish’s research primarily focuses on the modeling, simulation, and device-circuit co-design of upcoming and emerging nanoscale technologies.

Before his current role, Girish held multiple positions in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley including assistant professional researcher, postdoctoral scholar, and research and development engineer. He also served as the inaugural executive director of the Berkeley Device Modeling Center (BDMC) and made significant contributions to the BSIM suite of compact models. His notable works include the development of industry-focused compact models for cryogenic CMOS operation, ferroelectric devices, high-voltage MOSFETs, and thin film transistors.

Girish has received several prestigious awards, including the IEEE EDS Early Career Award (2022), the Outstanding Ph.D. Thesis Award from IIT Kanpur (2020), and the Best Paper Award at the IEEE International Conference on Emerging Electronics (2016). He is an active member of the IEEE EDS Compact Modeling Committee and the IEEE EDS Electronic Materials Committee. He has served as a reviewer for several journals and conferences and has been part of the technical program committee for the IEEE Electron Devices Technology and Manufacturing (EDTM) conference.

Girish earned his Ph.D. and master’s degrees in electrical engineering from the Indian Institute of Technology (IIT) Kanpur and his bachelor’s degree in electronics and communication engineering from Delhi Technological University.

Amol D. Gaidhane is a Postdoctoral Research Scholar with the School of Electrical, Computer and Energy Engineering at Arizona State University, Tempe, United States. His research interests include data-driven compact models of semiconductor devices and cryogenic semiconductor CMOS devices.

Hussam Amrouch is a Professor of AI Processor Design at the Technical University of Munich, Munich, Germany. His research interests are ultra-efficient embodied AI, reliable and secure designs in cutting-edge technologies, and cryogenic circuits that pave the way for large-scale quantum computers.

Yogesh Singh Chauhan is a Chair professor in the department of electrical engineering at Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices. He is the Fellow of IEEE and Indian National Academy of Engineering. He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the chairperson of IEEE U.P. section and IEEE-EDS Compact Modeling Committee. He has published more than 400 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.